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| author | Lei Huang <lei@ca.ibm.com> | 2018-04-18 17:41:46 +0000 |
|---|---|---|
| committer | Lei Huang <lei@ca.ibm.com> | 2018-04-18 17:41:46 +0000 |
| commit | 192c6ccf6db3799305e2e150abcfc24de608e165 (patch) | |
| tree | 759602b0d13156cfb69a9acae3814bcac986cd4f /llvm/lib/Target | |
| parent | 3a83c5c9f7414220e66c6cd293716a7e13fd2c23 (diff) | |
| download | bcm5719-llvm-192c6ccf6db3799305e2e150abcfc24de608e165.tar.gz bcm5719-llvm-192c6ccf6db3799305e2e150abcfc24de608e165.zip | |
[Power9]Legalize and emit code for converting Unsigned HWord/Char to Quad-Precision
Legalize and emit code for converting unsigned HWord/Char to QP:
xscvsdqp
xscvudqp
Only covering patterns for unsigned forms cause we don't have part-word
sign-extending integer loads into VSX registers.
Differential Revision: https://reviews.llvm.org/D45494
llvm-svn: 330278
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrVSX.td | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 1fb020b3876..1907b2766fb 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -3142,6 +3142,14 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { def : Pat<(f128 (uint_to_fp (i64 (load ixaddr:$src)))), (f128 (XSCVUDQP (LXSD ixaddr:$src)))>; + // Convert Unsigned HWord in memory -> QP + def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi16)), + (f128 (XSCVUDQP (LXSIHZX xaddr:$src)))>; + + // Convert Unsigned Byte in memory -> QP + def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi8)), + (f128 (XSCVUDQP (LXSIBZX xoaddr:$src)))>; + } // end HasP9Vector, AddedComplexity let Predicates = [HasP9Vector] in { |
