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* Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-1735-95/+116
| | | | | | | This is a mechanical change of comments in switches like fallthrough, fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead. llvm-svn: 278902
* [ppc64] Don't apply sibling call optimization if callee has any byval argChuang-Yu Cheng2016-08-171-1/+8
| | | | | | | | | | | | | | | This is a quick work around, because in some cases, e.g. caller's stack size > callee's stack size, we are still able to apply sibling call optimization even callee has any byval arg. This patch fix: https://llvm.org/bugs/show_bug.cgi?id=28328 Reviewers: hfinkel kbarton nemanjai amehsan Subscribers: hans, tjablin https://reviews.llvm.org/D23441 llvm-svn: 278900
* [PM] Port the always inliner to the new pass manager in a much moreChandler Carruth2016-08-171-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | minimal and boring form than the old pass manager's version. This pass does the very minimal amount of work necessary to inline functions declared as always-inline. It doesn't support a wide array of things that the legacy pass manager did support, but is alse ... about 20 lines of code. So it has that going for it. Notably things this doesn't support: - Array alloca merging - To support the above, bottom-up inlining with careful history tracking and call graph updates - DCE of the functions that become dead after this inlining. - Inlining through call instructions with the always_inline attribute. Instead, it focuses on inlining functions with that attribute. The first I've omitted because I'm hoping to just turn it off for the primary pass manager. If that doesn't pan out, I can add it here but it will be reasonably expensive to do so. The second should really be handled by running global-dce after the inliner. I don't want to re-implement the non-trivial logic necessary to do comdat-correct DCE of functions. This means the -O0 pipeline will have to be at least 'always-inline,global-dce', but that seems reasonable to me. If others are seriously worried about this I'd like to hear about it and understand why. Again, this is all solveable by factoring that logic into a utility and calling it here, but I'd like to wait to do that until there is a clear reason why the existing pass-based factoring won't work. The final point is a serious one. I can fairly easily add support for this, but it seems both costly and a confusing construct for the use case of the always inliner running at -O0. This attribute can of course still impact the normal inliner easily (although I find that a questionable re-use of the same attribute). I've started a discussion to sort out what semantics we want here and based on that can figure out if it makes sense ta have this complexity at O0 or not. One other advantage of this design is that it should be quite a bit faster due to checking for whether the function is a viable candidate for inlining exactly once per function instead of doing it for each call site. Anyways, hopefully a reasonable starting point for this pass. Differential Revision: https://reviews.llvm.org/D23299 llvm-svn: 278896
* Some places that could using TargetParser in LLVM. NFC.Zijiao Ma2016-08-172-3/+8
| | | | llvm-svn: 278888
* ARM: Avoid dereferencing end() in ARMFrameLowering::emitPrologueDuncan P. N. Exon Smith2016-08-171-1/+2
| | | | | | | | llvm::tryFoldSPUpdateIntoPushPop assumes its arguments are valid MachineInstrs. Update ARMFrameLowering::emitPrologue to respect that; when LastPush==end(), it can't possibly be a push instruction anyway. llvm-svn: 278880
* Hexagon: Avoid dereferencing end() in HexagonInstrInfo::InsertBranchDuncan P. N. Exon Smith2016-08-171-7/+5
| | | | llvm-svn: 278878
* AMDGPU: Avoid looking for the DebugLoc in end()Duncan P. N. Exon Smith2016-08-171-14/+12
| | | | | | | The end() iterator isn't a safe thing to dereference. Pass the DebugLoc into EmitFetchClause and EmitALUClause to avoid it. llvm-svn: 278873
* [AMDGPU] Remove duplicate initialization of SIDebuggerInsertNops passKonstantin Zhuravlyov2016-08-161-1/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D23556 llvm-svn: 278863
* [x86] Allow merging multiple instances of an immediate within a basic block ↵Sanjay Patel2016-08-162-6/+9
| | | | | | | | | | | | | | for code size savings, for 64-bit constants. This patch handles 64-bit constants which can be encoded as 32-bit immediates. It extends the functionality added by https://reviews.llvm.org/D11363 for 32-bit constants to 64-bit constants. Patch by Sunita Marathe! Differential Revision: https://reviews.llvm.org/D23391 llvm-svn: 278857
* [AArch64] Adjust the scheduling model for Exynos M1.Evandro Menezes2016-08-161-14/+9
| | | | | | Refine the model for the FP division unit. llvm-svn: 278846
* [AArch64] Adjust the scheduling model for Exynos M1.Evandro Menezes2016-08-161-7/+11
| | | | | | Refine the model for the integer division unit. llvm-svn: 278845
* AMDGPU: Remove excessive padding from ImmOp and RegOp.Matt Arsenault2016-08-161-4/+4
| | | | | | | | | | | The structs ImmOp and RegOp are in AArch64AsmParser.cpp (inside anonymous namespace). This diff changes the order of fields and removes the excessive padding (8 bytes). Patch by Alexander Shaposhnikov llvm-svn: 278844
* [Hexagon] Standardize next batch of pseudo instructionsKrzysztof Parzyszek2016-08-1610-74/+67
| | | | | | | | | | | | | ALIGNA PS_aligna ALLOCA PS_alloca TFR_FI PS_fi TFR_FIA PS_fia TFR_PdFalse PS_false TFR_PdTrue PS_true VMULW PS_vmulw VMULW_ACC PS_vmulw_acc llvm-svn: 278832
* [mips] Enforce compact branch restrictionsSimon Dardis2016-08-161-13/+12
| | | | | | | | | | | Check both operands for use of the $zero register which cannot be used with a compact branch instruction. Reviewers: dsanders, vkalintris Differential Review: https://reviews.llvm.org/D23547 llvm-svn: 278824
* [Hexagon] Clean up some miscellaneous V60 intrinsics a bitKrzysztof Parzyszek2016-08-166-69/+58
| | | | llvm-svn: 278823
* [Hexagon] Standardize vector predicate load/store pseudo instructionsKrzysztof Parzyszek2016-08-163-67/+32
| | | | | | | | | | | | - Remove unused instructions: LDriq_pred_vec_V6, STriq_pred_vec_V6, and the 128B counterparts. - Rename: LDriq_pred_V6 PS_vloadrq_ai LDriq_pred_V6_128B PS_vloadrq_ai_128B STriq_pred_V6 PS_vstorerq_ai STriq_pred_V6_128B PS_vstorerq_ai_128B llvm-svn: 278813
* [AArch64][GlobalISel] Select G_MUL.Ahmed Bougacha2016-08-161-0/+37
| | | | llvm-svn: 278810
* [AArch64][GlobalISel] Factor out unsupported binop check. NFC.Ahmed Bougacha2016-08-161-40/+50
| | | | | | | We're going to need it for G_MUL, and, if other targets end up using something similar, we can easily put it in the generic selector. llvm-svn: 278808
* [AArch64][GlobalISel] Select (variable) shifts.Ahmed Bougacha2016-08-162-0/+19
| | | | | | For now, no support for immediates. llvm-svn: 278804
* [AArch64][GlobalISel] Select p0 G_FRAME_INDEX.Ahmed Bougacha2016-08-162-0/+20
| | | | | | And mark it as legal. llvm-svn: 278802
* [x86] Refactor a PowerPC specific ctlz/srl transformation (NFC).Pierre Gousseau2016-08-162-13/+7
| | | | | | | | Following the discussion on D22038, this refactors a PowerPC specific setcc -> srl(ctlz) transformation so it can be used by other targets. Differential Revision: https://reviews.llvm.org/D23445 llvm-svn: 278799
* [X86][SSE] Add support for combining v2f64 target shuffles to VZEXT_MOVL ↵Simon Pilgrim2016-08-161-3/+3
| | | | | | | | byte rotations The combine was only matching v2i64 as it assumed lowering to MOVQ - but we have v2f64 patterns that match in a similar fashion llvm-svn: 278794
* Correct the upper bound for a CBZ/CBNZ branch target.Prakhar Bahuguna2016-08-161-2/+4
| | | | | | | | | | | | | Summary: Fix for the upper bound check that was causing a build failure. Reviewers: olista01, rengolin, t.p.northover Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23501 llvm-svn: 278789
* [Thumb] Validate branch target for CBZ/CBNZ instructions.Prakhar Bahuguna2016-08-162-0/+11
| | | | | | | | | | | | | | | | | Summary: The assembler currently does not check the branch target for CBZ/CBNZ instructions, which only permit branching forwards with a positive offset. This adds validation for the branch target to ensure negative PC-relative offsets are not encoded into the instruction, whether specified as a literal or as an assembler symbol. Reviewers: rengolin, t.p.northover Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D23312 llvm-svn: 278788
* [X86][SSE] Add support for combining target shuffles to PALIGNR byte rotationsSimon Pilgrim2016-08-161-22/+55
| | | | llvm-svn: 278787
* [AVR] Fix compile errorsJob Noorman2016-08-162-5/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D23450 llvm-svn: 278784
* [X86] Add xgetbv/xsetbv intrinsics to non-windows platformsGuy Blank2016-08-163-3/+61
| | | | | | Differential Revision: https://reviews.llvm.org/D21958 llvm-svn: 278782
* [AMDGPU] Give enum an explicit 64-bit type to fix MSVC 2013 failuresReid Kleckner2016-08-151-1/+1
| | | | | | | | | | Recall that MSVC always gives enums the type 'int', nothing else. MSVC 2015 does not appear to have this problem anymore. Clang-cl -Wmicrosoft-enum-value flags this, FWIW, so now I have a true positive for my warning. :) llvm-svn: 278762
* AMDGPU/R600: Convert buffer id to VTX_READ inputJan Vesely2016-08-154-183/+110
| | | | | | | | | Use patterns instead of multiple instructions Add buffer id to asm string https://reviews.llvm.org/D22650 llvm-svn: 278749
* Revert "[Thumb] Validate branch target for CBZ/CBNZ instructions."Matthias Braun2016-08-152-11/+0
| | | | | | | | | | | This currently breaks the greendragon clang-stage1-configure-RA/ and brotli. It is probably just uncovering a pre-existing problem. Reverting temporarily to get the buildbots green again. A reduced testcase will follow shortly. This reverts commit r278659. llvm-svn: 278711
* AMDGPU: Update AMDGPURuntimeMetadata.h for enums of address space qualifiersYaxun Liu2016-08-151-0/+7
| | | | llvm-svn: 278682
* AMDGPU: Don't fold subregister extracts into tied operandsMatt Arsenault2016-08-151-3/+15
| | | | llvm-svn: 278676
* [AMDGPU] fix failure on printing of non-existing instruction operands.Valery Pykhtin2016-08-151-0/+5
| | | | | | Differential revision: https://reviews.llvm.org/D23323 llvm-svn: 278665
* MachineLoop: add methods findLoopControlBlock and findLoopPreheaderSjoerd Meijer2016-08-151-62/+11
| | | | | | | | | | | This adds two new utility functions findLoopControlBlock and findLoopPreheader to MachineLoop and MachineLoopInfo. These functions are refactored and taken from the Hexagon target as they are target independent; thus this is intendend to be a non-functional change. Differential Revision: https://reviews.llvm.org/D22959 llvm-svn: 278661
* [Thumb] Validate branch target for CBZ/CBNZ instructions.Prakhar Bahuguna2016-08-152-0/+11
| | | | | | | | | | | | | | | | | Summary: The assembler currently does not check the branch target for CBZ/CBNZ instructions, which only permit branching forwards with a positive offset. This adds validation for the branch target to ensure negative PC-relative offsets are not encoded into the instruction, whether specified as a literal or as an assembler symbol. Reviewers: rengolin, t.p.northover Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D23312 llvm-svn: 278659
* [X86] PADDUSB/W instructions should be commutable.Craig Topper2016-08-151-2/+2
| | | | llvm-svn: 278654
* [X86] Mark some of the X86 SDNodes as commutative.Craig Topper2016-08-151-8/+10
| | | | llvm-svn: 278653
* [X86] X86ISD::FANDN is not commutative or associative.Craig Topper2016-08-151-2/+1
| | | | llvm-svn: 278652
* [AVX-512] Mark VPMADDWD as commutable to match SSE/AVX version.Craig Topper2016-08-141-7/+8
| | | | llvm-svn: 278629
* [AVX-512] Add masked commutable floating point max/min instructions to ↵Craig Topper2016-08-141-0/+24
| | | | | | folding tables. llvm-svn: 278628
* [AVX-512] Add masked logical operations to memory folding tables.Craig Topper2016-08-141-2/+98
| | | | llvm-svn: 278627
* [AVX512] Fix VFPCLASSSD/VFPCLASSSS intrinsic lowering. The i1 result should ↵Igor Breger2016-08-141-1/+1
| | | | | | | | be zero extended according to SPEC. Differential Revision: http://reviews.llvm.org/D23489 llvm-svn: 278626
* [AVX512] Fix insertelement i1 lowering.Igor Breger2016-08-142-14/+67
| | | | | | | | | 1. Use shuffle to insert element i1 into vector. The previous implementation was incorrect ( dest_bit OR src_bit , it doesn't clear the bit if src_bit=0 ) 2. Improve shuffle i1 vector, use CVT2MASK if supported instead TRUNCATE. Differential Revision: http://reviews.llvm.org/D23347 llvm-svn: 278623
* Fix unsupported relocation type R_HEX_6_X' for symbol .rodataRon Lieberman2016-08-131-2/+9
| | | | | | | | | | | LowerTargetConstantPool is not properly setting the TargetFlag to indicate desired relocation. Coding error, the offset parameter was omitted, so the TargetFlag was used as the offset, and the TargetFlag defaulted to zero. This only affects -fpic compilation, and only those items created in a Constant Pool, for example a vector of constants. Halide ran into this issue. llvm-svn: 278614
* [X86] Add a check of isCommutable at the top of ↵Craig Topper2016-08-131-0/+3
| | | | | | | | X86InstrInfo::findCommutedOpIndices. Most callers don't check if the instruction is commutable before calling. This saves us the trouble of ending up in the default of the switch and having to determine if this is an FMA or not. llvm-svn: 278597
* [AVX-512] Add isCommutable to scalar FMA3 instructions.Craig Topper2016-08-131-5/+5
| | | | llvm-svn: 278596
* [AVX-512] Add commutable flags to 132 form FMA3 instructions.Craig Topper2016-08-131-3/+3
| | | | llvm-svn: 278595
* [X86] Remove patterns for (vzmovl (insert_subvector undef, ↵Craig Topper2016-08-131-11/+0
| | | | | | (scalar_to_vector))) as the (vzmovl VR256) pattern has higher priority. NFC llvm-svn: 278594
* [AVX-512] Remove an AddedComplexity that was prioritizing basic vzmovl ↵Craig Topper2016-08-131-1/+1
| | | | | | patterns over more complex ones that produce better code. llvm-svn: 278593
* [AVX-512] Add patterns to support VZEXT_MOVL from 512-bit vectors with ↵Craig Topper2016-08-131-1/+16
| | | | | | | | 64-bit and 32-bit elements. Fixes PR28961. llvm-svn: 278592
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