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* Recommit r317904: [Hexagon] Create HexagonISelDAGToDAG.h, NFCKrzysztof Parzyszek2017-11-102-109/+139
* AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.tdKonstantin Zhuravlyov2017-11-104-218/+258
* Revert "[Hexagon] Create HexagonISelDAGToDAG.h, NFC"Krzysztof Parzyszek2017-11-102-139/+109
* [X86] Merge the template method selectAddrOfGatherScatterNode into selectVect...Craig Topper2017-11-101-25/+16
* [RISCV] Silence an unused variable warning in release builds [NFC]Mandeep Singh Grang2017-11-102-5/+5
* [Hexagon] Create HexagonISelDAGToDAG.h, NFCKrzysztof Parzyszek2017-11-102-109/+139
* [RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints.Jonas Paulsson2017-11-105-4/+99
* [X86] Add support for combining FMADDSUB(A, B, FNEG(C))->FMSUBADD(A, B, C)Craig Topper2017-11-101-0/+31
* [AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environ...Yaxun Liu2017-11-101-3/+7
* [AMDGPU] Fix pointer info for pseudo source for r600Yaxun Liu2017-11-102-0/+21
* [SystemZ] Add support for the "o" inline asm constraintUlrich Weigand2017-11-092-0/+5
* [mips] Correct microMIP's jump and add unconditional branch pseudoSimon Dardis2017-11-094-18/+29
* [RISCV] MC layer support for the standard RV32A instruction set extensionAlex Bradbury2017-11-096-12/+128
* [RISCV] MC layer support for the standard RV32M instruction set extensionAlex Bradbury2017-11-094-4/+45
* Sched model improving on btver2: JFPU01 resource, vtestp* for xmm.Andrew V. Tischenko2017-11-091-11/+26
* Add -print-schedule scheduling comments to inline asm.Andrew V. Tischenko2017-11-093-14/+16
* [X86] Give priority to EVEX FMA instructions over FMA4 instructions.Craig Topper2017-11-093-63/+69
* Fix "default label in switch which covers all enumeration values" warningVitaly Buka2017-11-091-2/+0
* [X86] Make X86ISD::FMADDS3 isel patterns commutable.Craig Topper2017-11-091-4/+4
* AMDGPU: Merge BUFFER_STORE_DWORD_OFFEN/OFFSET into x2, x4Marek Olsak2017-11-091-4/+109
* AMDGPU: Lower buffer store and atomic intrinsics manuallyMarek Olsak2017-11-095-20/+206
* AMDGPU: Merge BUFFER_LOAD_DWORD_OFFSET into x2, x4Marek Olsak2017-11-091-13/+37
* AMDGPU: Merge BUFFER_LOAD_DWORD_OFFEN into x2, x4Marek Olsak2017-11-091-26/+141
* AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4Marek Olsak2017-11-092-14/+125
* AMDGPU: Fold immediate offset into BUFFER_LOAD_DWORD lowered from SMEMMarek Olsak2017-11-093-14/+40
* [X86] Make sure we don't read too many operands from X86ISD::FMADDS1/FMADDS3 ...Craig Topper2017-11-091-2/+5
* [X86] X86MaskedGatherSDNode shouldn't inherit from MaskedGatherScatterSDNodeCraig Topper2017-11-081-2/+10
* [X86] Preserve memory refs when folding loads into divides.Craig Topper2017-11-081-1/+5
* [X86] Remove an if check on the result of a cast. NFCCraig Topper2017-11-081-12/+6
* Revert "Correct dwarf unwind information in function epilogue for X86"Reid Kleckner2017-11-083-54/+0
* Set hasSideEffects=0 for PHI and fix affected passesAlex Bradbury2017-11-081-3/+2
* [X86] Correct the implementation of BEXTR load folding to use the shift as th...Craig Topper2017-11-081-6/+14
* [WebAssembly] Update test expectationsSam Clegg2017-11-081-14/+3
* [X86] Don't call validateInstruction from MatchAndEmitInstruction when Matchi...Craig Topper2017-11-081-2/+2
* [WebAssembly] Call signExtend to get sign extended registerDan Gohman2017-11-081-1/+1
* [WebAssembly] Revise the strategy for inline asm.Dan Gohman2017-11-082-6/+25
* [RISCV] Initial support for function callsAlex Bradbury2017-11-088-4/+186
* [RISCV] Codegen for conditional branchesAlex Bradbury2017-11-088-4/+118
* [RISCV] Codegen support for memory operations on global addressesAlex Bradbury2017-11-085-22/+99
* [RISCV] Codegen support for memory operationsAlex Bradbury2017-11-084-0/+47
* [RISCV] Codegen support for materializing constantsAlex Bradbury2017-11-081-0/+24
* [mips] Guard indirect and tailcall pseudo instructions correctly.Simon Dardis2017-11-083-11/+23
* [NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0Alex Bradbury2017-11-081-3/+1
* [X86] Add patterns to fold EVEX store with EVEX encoded vcvtps2ph instruction...Craig Topper2017-11-081-11/+23
* [X86] Allow legacy vcvtps2ph intrinsics to select EVEX encoded instructions. ...Craig Topper2017-11-082-18/+16
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-0886-99/+99
* AMDGPU: Set correct sched model on v_mad_u64_u32Matt Arsenault2017-11-081-0/+2
* Attribute nonlazybind should not affect calls to functions with hidden visibi...Sriraman Tallam2017-11-082-9/+11
* [NVPTX] Implement __nvvm_atom_add_gen_d builtin.Justin Lebar2017-11-072-0/+14
* Use new vector insert half-word and byte instructions when we see inserteleme...Graham Yiu2017-11-072-3/+33
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