summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Expand)AuthorAgeFilesLines
* AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsicsMatt Arsenault2019-06-186-21/+156
* AMDGPU: Change API for checking for exec modificationMatt Arsenault2019-06-184-27/+55
* AMDGPU: Fold readlane from copy of SGPR or immMatt Arsenault2019-06-182-0/+42
* AMDGPU: Remove unnecessary check for virtual registerMatt Arsenault2019-06-181-17/+4
* AMDGPU: Fix iterator crash in AMDGPUPromoteAllocaMatt Arsenault2019-06-181-5/+9
* AMDGPU/GlobalISel: RegBankSelect for amdgcn.div.scaleMatt Arsenault2019-06-181-0/+14
* [ARM] Some Thumb2ITBlock clean ups. NFCSjoerd Meijer2019-06-182-48/+41
* [SystemZ] Fix AHIMuxK pseudo expansion.Jonas Paulsson2019-06-181-4/+6
* [AMDGPU] Speed up live-in virtual register set computaion in GCNScheduleDAGMI...Valery Pykhtin2019-06-184-5/+80
* [X86] Replace any_extend* vector extensions with zero_extend* equivalentsSimon Pilgrim2019-06-183-84/+53
* [X86] Move code that shrinks immediates for ((x << C1) op C2) into a helper f...Craig Topper2019-06-181-108/+118
* [X86] Remove MOVDI2SSrm/MOV64toSDrm/MOVSS2DImr/MOVSDto64mr CodeGenOnly instru...Craig Topper2019-06-183-64/+12
* [X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.Craig Topper2019-06-187-58/+129
* [GlobalISel][Localizer] Rewrite localizer to run in 2 phases, inter & intra b...Amara Emerson2019-06-171-0/+4
* Use VR128X instead of FR32X/FR64X for the register class in VMOVSSZmrk/VMOVSD...Craig Topper2019-06-171-5/+5
* [X86] Make an assert in LowerSCALAR_TO_VECTOR stricter to make it clear what ...Craig Topper2019-06-171-1/+2
* [AMDGPU] Use custom inserter for gfx10 VOP2bStanislav Mekhanoshin2019-06-171-1/+3
* [AMDGPU] Propagate function attributes thru bitcastsStanislav Mekhanoshin2019-06-171-3/+4
* AMDGPU/GFX10: Don't generate s_code_end padding in the asm-printerNicolai Haehnle2019-06-171-1/+7
* [GlobalISel][AArch64] Fold G_SUB into G_ICMP when it's safe to do soJessica Paquette2019-06-171-16/+144
* [X86] Add TB_NO_REVERSE to some memory folding table entries where the regist...Craig Topper2019-06-171-3/+3
* [X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026)Simon Pilgrim2019-06-171-0/+45
* [AMDGPU] gfx1010 wavefrontsize intrinsic foldingStanislav Mekhanoshin2019-06-173-16/+59
* [AMDGPU] Pass to propagate ABI attributes from kernels to the functionsStanislav Mekhanoshin2019-06-174-4/+356
* [X86][AVX] Split under-aligned vector nt-stores.Simon Pilgrim2019-06-171-2/+13
* [LV] Suppress vectorization in some nontemporal casesWarren Ristow2019-06-172-0/+37
* GlobalISel: Verify intrinsicsMatt Arsenault2019-06-171-26/+34
* AMDGPU/GlobalISel: Account for multiple defs when finding intrinsic IDMatt Arsenault2019-06-171-2/+1
* [AMDGPU] gfx1010 wave32 metadataStanislav Mekhanoshin2019-06-178-2/+85
* AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECTTom Stellard2019-06-173-1/+195
* [X86] combineLoad - begun making the load split code more generic. NFCI.Simon Pilgrim2019-06-171-13/+12
* [X86][SSE] Prevent misaligned non-temporal vector load/store combinesSimon Pilgrim2019-06-171-4/+13
* AMDGPU: Ignore subtarget for InferAddressSpacesMatt Arsenault2019-06-171-2/+1
* AMDGPU/GlobalISel: Fix default mapping for non-register operandsMatt Arsenault2019-06-171-1/+5
* AMDGPU: Cleanup custom PseudoSourceValue definitionsMatt Arsenault2019-06-171-16/+23
* [CodeGen] Check for HardwareLoop Latch ExitBlockSam Parker2019-06-171-4/+0
* [DAGCombiner] [CodeGenPrepare] More comprehensive GEP splittingLuis Marques2019-06-171-0/+1
* Fix clang -Wcovered-switch-default after stack-id change by D60137Fangrui Song2019-06-171-8/+7
* [ARM] Fix another -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds af...Fangrui Song2019-06-171-1/+1
* [ARM] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after D63265Fangrui Song2019-06-171-1/+1
* Describe stack-id as an enumSander de Smalen2019-06-174-10/+16
* [ARM] Remove ARMComputeBlockSizeSam Parker2019-06-171-80/+0
* [ARM] Add ARMBasicBlockInfo.cppSam Parker2019-06-171-0/+146
* [ARM] Extract some code from ARMConstantIslandPassSam Parker2019-06-174-112/+101
* PowerPC: Optimize SPE double parameter calling setupJustin Hibbits2019-06-176-49/+172
* [X86] Add TB_NO_REVERSE to some folding table entries where the register from...Craig Topper2019-06-161-9/+9
* AMDGPU: Prepare for explicit absolute relocations in code generationNicolai Haehnle2019-06-164-8/+24
* AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0Nicolai Haehnle2019-06-163-10/+19
* AMDGPU/GFX10: Support DLC bit in llvm.amdgcn.s.buffer.load intrinsicNicolai Haehnle2019-06-164-13/+22
* [AMDGPU] gfx10 conditional registers handlingStanislav Mekhanoshin2019-06-1618-211/+599
OpenPOWER on IntegriCloud