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* Revert "[mips] Fix assertion on i128 addition/subtraction on MIPS64"Vasileios Kalintiris2015-01-262-37/+5
* Correct the header guard for MipsABIInfo.h.Eric Christopher2015-01-261-2/+2
* Fix a problem where the AArch64 ELF assembler was failing withEric Christopher2015-01-261-1/+2
* [PowerPC] Reset the baseline for ppc64le to be equivalent to pwr8Bill Schmidt2015-01-251-14/+30
* AVX-512: Changes in operations on masks registers for KNL and SKXElena Demikhovsky2015-01-253-14/+53
* [X86] Give scalar VRNDSCALE instructions priority in AVX512 mode.Craig Topper2015-01-252-20/+26
* Simplify a multiclass. No functional change.Craig Topper2015-01-251-14/+18
* Remove tab characters. NFCCraig Topper2015-01-251-1/+1
* Implemented cost model for masked load/store operations.Elena Demikhovsky2015-01-251-0/+57
* [X86] Replace i32i8imm on SSE/AVX instructions with i32u8imm which will make ...Craig Topper2015-01-254-30/+38
* [X86] Use u8imm in several places that used i32i8imm that don't require an i3...Craig Topper2015-01-252-20/+20
* Remove tab characters. NFC.Craig Topper2015-01-251-1/+1
* BPF backendAlexei Starovoitov2015-01-2444-1/+3266
* [mips] Fix 'jumpy' debug line info around calls.Daniel Sanders2015-01-243-39/+35
* [mips] Fix assertion on i128 addition/subtraction on MIPS64Daniel Sanders2015-01-242-5/+37
* [PM] Rework how the TargetLibraryInfo pass integrates with the new passChandler Carruth2015-01-241-4/+4
* [AArch64][LoadStoreOptimizer] Form LDPSW when possible.Quentin Colombet2015-01-241-1/+15
* [x86] Fix a commentBruno Cardoso Lopes2015-01-241-1/+1
* R600/SI: Emit .hsa.version section for amdhsa OSTom Stellard2015-01-231-1/+13
* [x86] Combine x86mmx/i64 to v2i64 conversion to use scalar_to_vectorBruno Cardoso Lopes2015-01-231-0/+29
* R600/SI: Move i64 -> v2i32 load promotion into AMDGPUDAGToDAGISel::Select()Tom Stellard2015-01-232-3/+22
* [mips] fix spelling of 'disassembler'Alexei Starovoitov2015-01-231-3/+3
* Classify functions by EH personality type rather than using the tripleReid Kleckner2015-01-231-4/+2
* Remove some local variables in place of just querying for themEric Christopher2015-01-231-6/+4
* [mips] Add new error message and improve testing for parsing the .module dire...Toma Tabacu2015-01-231-26/+27
* This patch fixes issue with lowering below mentioned pattern :-Jyoti Allur2015-01-231-7/+10
* [x86] Change u8imm operands to always print as unsigned. This makes shuffle m...Craig Topper2015-01-235-0/+15
* [X86] Add IntrNoMem to the AVX512 conflict intrinsics.Craig Topper2015-01-231-1/+9
* Reformat.NAKAMURA Takumi2015-01-231-3/+2
* MipsAsmParser.cpp: Suppress a warning introduced in r226657. [-Wunused-variable]NAKAMURA Takumi2015-01-231-3/+2
* R600: Try to use lower types for 64bit division if possibleJan Vesely2015-01-222-13/+39
* R600: Simplify LowerUDIVREMJan Vesely2015-01-221-19/+11
* [X86][AVX] Added (V)MOVDDUP / (V)MOVSLDUP / (V)MOVSHDUP memory folding + tests.Simon Pilgrim2015-01-221-2/+5
* AArch64: decode all MRS/MSR forms early to avoid saving FeatureBits.Tim Northover2015-01-221-42/+35
* Mark |TLI| variables used to suppress -Wunused-variable warnings.Alexander Potapenko2015-01-221-0/+2
* Fixed a bug in type legalizer for masked load/store intrinsics.Elena Demikhovsky2015-01-221-0/+164
* Revert r226798. Guess I missed the patterns.Craig Topper2015-01-221-2/+2
* Use u8imm instead of i32i8imm on a couple instructions that have no patterns ...Craig Topper2015-01-221-2/+2
* [X86] Remove some unused multiclasses from AVX512 instruction file.Craig Topper2015-01-221-101/+0
* ARM: fail less catastrophically on invalid Windows inputSaleem Abdulrasool2015-01-222-5/+15
* [X86][SSE] Missing SSE/AVX1 memory folding integer instructionsSimon Pilgrim2015-01-211-1/+57
* [X86][SSE] Added support for SSE3 lane duplication shuffle instructionsSimon Pilgrim2015-01-212-25/+37
* Fix load-store optimizer on thumbv4tJonathan Roelofs2015-01-211-3/+14
* [X86][SSE] movddup shuffle mask decodesSimon Pilgrim2015-01-213-18/+52
* R600/SI: Custom lower froundMatt Arsenault2015-01-214-24/+117
* [Hexagon] Converting multiply and accumulate with immediate intrinsics to pat...Colin LeMahieu2015-01-211-0/+21
* [X86] Declare SSE4.1/AVX2 vector extloads covered by PMOV[SZ]X legal.Ahmed Bougacha2015-01-212-9/+70
* AArch64: add backend option to reserve x18 (platform register)Tim Northover2015-01-211-3/+7
* [x32] Fast ISel should use LEA64_32r instead of LEA32r to adjust addresses in...Michael Kuperstein2015-01-211-2/+8
* [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction BJozef Kolek2015-01-2111-1/+153
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