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* Simplify code.Jakub Staszak2012-12-061-3/+1
* Remove intrinsic specific instructions for (V)MOVQUmr with patterns pointing ...Craig Topper2012-12-061-13/+5
* Mark MOVDQ(A/U)rm as ReMaterializable. Mark all MOVDQ(A/U) instructions as ne...Craig Topper2012-12-062-4/+9
* [arm fast-isel] Make the fast-isel implementation of memcpy respect alignment.Chad Rosier2012-12-061-11/+22
* Let targets provide hooks that compute known zero and ones for any_extendEvan Cheng2012-12-064-0/+73
* Define new-value store instructions with base+immediate addressing modeJyotsna Verma2012-12-051-128/+53
* Cost Model: change the default cost of control flow instructions (br / ret / ...Nadav Rotem2012-12-051-1/+1
* Correct ARM NOP encodingDavid Sehr2012-12-051-1/+1
* [NVPTX] Fix crash with unnamed struct argumentsJustin Holewinski2012-12-051-1/+1
* Use multiclass to define store instructions with base+immediate offsetJyotsna Verma2012-12-051-138/+68
* Fix misplaced closing brace.Matthew Curtis2012-12-051-1/+2
* Added a option to the disassembler to print immediates as hex.Kevin Enderby2012-12-052-11/+11
* Simplified BLEND pattern matching for shuffles.Elena Demikhovsky2012-12-054-78/+68
* Add x86 isel lowering logic to form bit test with inverted condition. e.g.Evan Cheng2012-12-051-6/+17
* Appease GCC's -Wparentheses.Matt Beaumont-Gay2012-12-041-2/+2
* ARM custom lower ctpop for vector types. Patch by Pete Couperus.Evan Cheng2012-12-041-0/+117
* Define store instructions with base+register offset addressing modeJyotsna Verma2012-12-041-352/+116
* Make NaCl naming consistent. The triple OSType is called NaCl and is representedEli Bendersky2012-12-042-2/+2
* Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading...Jyotsna Verma2012-12-043-17/+97
* Add constant extender support to ALU32 instructions for V2.Jyotsna Verma2012-12-041-51/+79
* This patch introduces initial-exec model support for thread-local storageBill Schmidt2012-12-0413-15/+156
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-0449-100/+100
* Move all operand definitions into HexagonOperands.tdJyotsna Verma2012-12-042-53/+57
* Move generic Hexagon subtarget information into Hexagon.tdJyotsna Verma2012-12-042-64/+101
* Remove the old TRI::ResolveRegAllocHint() and getRawAllocationOrder() hooks.Jakob Stoklund Olesen2012-12-042-270/+0
* Classic JIT is still being supported by MIPS, along with MCJIT.Akira Hatanaka2012-12-033-11/+24
* Functions in MipsCodeEmitter.cpp that expand unaligned loads/stores are deadAkira Hatanaka2012-12-031-103/+0
* Implement ARMBaseRegisterInfo::getRegAllocationHints().Jakob Stoklund Olesen2012-12-032-0/+65
* Define store instructions with base+immediate offset addressing modeJyotsna Verma2012-12-032-185/+78
* Define load instructions with base+immediate offset addressing modeJyotsna Verma2012-12-031-203/+73
* Define unsigned const-ext predicates.Jyotsna Verma2012-12-031-0/+128
* Removing unnecessary 'else' statement from the predicates defined in HexagonO...Jyotsna Verma2012-12-031-48/+12
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-03181-798/+793
* Define signed const-ext predicates.Jyotsna Verma2012-12-031-0/+131
* Codegen failure for vmull with small vectorsSebastian Pop2012-11-301-13/+74
* Use multiclass for the load instructions with MEMri operand.Jyotsna Verma2012-11-301-184/+66
* This patch fixes the Altivec addend construction for the fused multiply-addAdhemerval Zanella2012-11-301-5/+7
* Switch LLVM_USE_RVALUE_REFERENCES to LLVM_HAS_RVALUE_REFERENCES.Chandler Carruth2012-11-301-1/+1
* Use multiclass for the store instructions with MEMri operand.Jyotsna Verma2012-11-302-163/+64
* Use multiclass for the load instructions with 'base + register offset'Jyotsna Verma2012-11-301-277/+97
* Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby2012-11-291-1/+7
* Add cortex-a5 subtarget to the supported ARM architecturesQuentin Colombet2012-11-292-1/+12
* rdar://12100355 (part 1)Shuxin Yang2012-11-293-1/+20
* Use multiclass for 'transfer' instructions.Jyotsna Verma2012-11-292-80/+98
* Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.Silviu Baranga2012-11-294-12/+102
* Allow targets to prefer TypeSplitVector over TypePromoteInteger when computin...Justin Holewinski2012-11-292-0/+7
* I changed hasAVX() to hasFp256() and hasAVX2() to hasInt256() in X86IselLower...Elena Demikhovsky2012-11-292-102/+104
* Define signed const-ext immediate operands and their predicates.Jyotsna Verma2012-11-282-0/+122
* ARM: Implement CanLowerReturn so large vectors get expanded into sret.Benjamin Kramer2012-11-282-0/+17
* Fix initial frame state on powerpc64.Ulrich Weigand2012-11-281-1/+1
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