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* Educate GetInstrSizeInBytes implementations thatDale Johannesen2010-04-074-0/+4
| | | | | | DBG_VALUE does not generate code. llvm-svn: 100681
* Remove late ARM codegen optimization pass committed by accident.Anton Korobeynikov2010-04-074-158/+1
| | | | | | It is not ready for public yet. llvm-svn: 100673
* Split A8/A9 itins - they already were too big.Anton Korobeynikov2010-04-073-603/+614
| | | | llvm-svn: 100672
* Add some crude itin approximation for VFP load / stores on A9Anton Korobeynikov2010-04-071-0/+54
| | | | llvm-svn: 100671
* Add some crude approximation for neon load/store instructionsAnton Korobeynikov2010-04-071-1/+55
| | | | llvm-svn: 100670
* Add some A8-based approximation for instructions with unknown cycle timesAnton Korobeynikov2010-04-071-0/+52
| | | | llvm-svn: 100669
* Move NEON-VFP domain fixer upper, so post-RA scheduler would benefit from it.Anton Korobeynikov2010-04-071-4/+6
| | | | llvm-svn: 100668
* Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack ↵Anton Korobeynikov2010-04-071-259/+266
| | | | | | anymore. llvm-svn: 100667
* Fix A8 FP NEON MAC itinsAnton Korobeynikov2010-04-071-2/+2
| | | | llvm-svn: 100666
* A9 NEON FP itinsAnton Korobeynikov2010-04-071-0/+66
| | | | llvm-svn: 100665
* Some permute goodness for A9Anton Korobeynikov2010-04-071-1/+85
| | | | llvm-svn: 100664
* More shift itins for A9Anton Korobeynikov2010-04-071-0/+21
| | | | llvm-svn: 100663
* More fixes for itinsAnton Korobeynikov2010-04-071-24/+26
| | | | llvm-svn: 100662
* Fix invalid itins for 32-bit varians of VMLAL and friendsAnton Korobeynikov2010-04-071-14/+14
| | | | llvm-svn: 100661
* Add MAC stuff for A9Anton Korobeynikov2010-04-071-1/+59
| | | | llvm-svn: 100660
* Fix invalid NEON MAC itins on A8Anton Korobeynikov2010-04-071-4/+4
| | | | llvm-svn: 100659
* Fix itins for VPALAnton Korobeynikov2010-04-071-3/+17
| | | | llvm-svn: 100658
* Fix itins for VABAAnton Korobeynikov2010-04-073-23/+76
| | | | llvm-svn: 100657
* Correct VMVN itinerary: operand is read in the second cycle, not in the first.Anton Korobeynikov2010-04-071-2/+2
| | | | llvm-svn: 100656
* More A9 itinerariesAnton Korobeynikov2010-04-072-2/+30
| | | | llvm-svn: 100655
* Correct itinerary class for VPADDAnton Korobeynikov2010-04-071-86/+40
| | | | llvm-svn: 100654
* VP{MAX, MIN} are of IIC_VSUBi4D itin class as well.Anton Korobeynikov2010-04-071-10/+35
| | | | llvm-svn: 100653
* VHADD differs from VHSUB at least on A9 - the former reads both operands in ↵Anton Korobeynikov2010-04-073-17/+71
| | | | | | the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP. llvm-svn: 100652
* Some easy NEON scheduling goodness for A9Anton Korobeynikov2010-04-071-1/+53
| | | | llvm-svn: 100651
* Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ↵Anton Korobeynikov2010-04-073-7/+38
| | | | | | ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( llvm-svn: 100650
* FCONST{S,D} behaves the same way as FP unary instructions. This is true for ↵Anton Korobeynikov2010-04-071-2/+2
| | | | | | both A8 and A9. llvm-svn: 100649
* Proper cycle times for locks, since wbck latency can be larger than fwd latency.Anton Korobeynikov2010-04-071-52/+57
| | | | llvm-svn: 100648
* Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9.Anton Korobeynikov2010-04-073-4/+20
| | | | llvm-svn: 100647
* Make use of new reserved/required scheduling stuff: introduce VFP and NEON ↵Anton Korobeynikov2010-04-072-22/+77
| | | | | | locks to model domain cross stalls precisly. llvm-svn: 100646
* Some bits of A9 scheduling: VFPAnton Korobeynikov2010-04-072-1/+102
| | | | llvm-svn: 100643
* Separate const from non-const stuff during mergeingAnton Korobeynikov2010-04-071-21/+35
| | | | llvm-svn: 100642
* Some initial version of global mergerAnton Korobeynikov2010-04-074-1/+144
| | | | llvm-svn: 100641
* Fix memory leaks for external symbol name strings.Sanjiv Gupta2010-04-073-20/+38
| | | | llvm-svn: 100601
* Clean up some signedness oddities in this code noticed by clang.John McCall2010-04-071-5/+6
| | | | llvm-svn: 100599
* Move printing of target-indepedent DEBUG_VALUE commentsDale Johannesen2010-04-071-48/+10
| | | | | | | into AsmPrinter. Target-dependent form is still generated by FastISel and still handled in X86 code. llvm-svn: 100596
* Fix a number of clang -Wsign-compare warnings that didn't have an obviousJohn McCall2010-04-063-3/+3
| | | | | | | solution. The only reason these don't fire with gcc-4.2 is that gcc turns off part of -Wsign-compare in C++ on accident. llvm-svn: 100581
* Revert 100573, it's causing some testsuite problems.Dale Johannesen2010-04-061-1/+67
| | | | llvm-svn: 100578
* Move printing of DEBUG_VALUE comments to target-independent place.Dale Johannesen2010-04-061-67/+1
| | | | | | There is probably a more elegant way to do this. llvm-svn: 100573
* Expand SELECT and SELECT_CC for NEON vector types.Bob Wilson2010-04-061-0/+2
| | | | | | Radar 7770501. llvm-svn: 100568
* Fix PR6696 and PR6663Jim Grosbach2010-04-065-14/+84
| | | | | | | | | | | | | | | | | When a frame pointer is not otherwise required, and dynamic stack alignment is necessary solely due to the spilling of a register with larger alignment requirements than the default stack alignment, the frame pointer can be both used as a general purpose register and a frame pointer. That goes poorly, for obvious reasons. This patch brings back a bit of old logic for identifying the use of such registers and conservatively reserves the frame pointer during register allocation in such cases. For now, implement for X86 only since it's 32-bit linux which is hitting this, and we want a targeted fix for 2.7. As a follow-on, this will be expanded to handle other targets, as theoretically the problem could arise elsewhere as well. llvm-svn: 100559
* Don't try to collapse DomainValues onto an incompatible SSE domain.Jakob Stoklund Olesen2010-04-061-4/+12
| | | | | | This fixes the Bullet regression on i386/nocona. llvm-svn: 100553
* Properly enable load clustering.Jakob Stoklund Olesen2010-04-051-4/+0
| | | | | | | Operand 2 on a load instruction does not have to be a RegisterSDNode for this to work. llvm-svn: 100497
* Fix ADD32rr_alt instruction encoding bug. Patch by Marius Wachtler.Evan Cheng2010-04-051-1/+1
| | | | llvm-svn: 100480
* Remove FIXME.Eric Christopher2010-04-051-2/+1
| | | | llvm-svn: 100466
* don't use emitlabel in the arm asm printer yet, the order Chris Lattner2010-04-051-2/+7
| | | | | | | isn't well specified. ARM really needs to have its instprinter finished at some point. llvm-svn: 100439
* fix a couple problems I introduced handling symbolsChris Lattner2010-04-051-4/+10
| | | | | | with spaces in them. Sym->getName() != OS << *Sym llvm-svn: 100434
* Disambiguate else.Benjamin Kramer2010-04-051-1/+2
| | | | llvm-svn: 100423
* unthread MMI from FastISelChris Lattner2010-04-053-8/+5
| | | | llvm-svn: 100416
* remove the MMI pointer from MachineFrameInfo.Chris Lattner2010-04-054-39/+28
| | | | llvm-svn: 100415
* simplify code.Chris Lattner2010-04-051-7/+4
| | | | llvm-svn: 100412
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