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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:21:16 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:21:16 +0000 |
| commit | 7ab31047a7f7342551ce4abb7098010f1d00f831 (patch) | |
| tree | 5e4363094fd6e2df84d723d192aa88fdf382f870 /llvm/lib/Target | |
| parent | 4d36f8890ffe41d1e787a25906f70e5dd70741ca (diff) | |
| download | bcm5719-llvm-7ab31047a7f7342551ce4abb7098010f1d00f831.tar.gz bcm5719-llvm-7ab31047a7f7342551ce4abb7098010f1d00f831.zip | |
More shift itins for A9
llvm-svn: 100663
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleV7.td | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleV7.td b/llvm/lib/Target/ARM/ARMScheduleV7.td index 39900a5d810..9b103a99abd 100644 --- a/llvm/lib/Target/ARM/ARMScheduleV7.td +++ b/llvm/lib/Target/ARM/ARMScheduleV7.td @@ -866,6 +866,27 @@ def CortexA9Itineraries : ProcessorItineraries<[ InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_NPipe]>], [3, 1, 1]>, // + // Quad-register Integer Shift + InstrItinData<IIC_VSHLiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [3, 1, 1]>, + // + // Double-register Integer Shift (4 cycle) + InstrItinData<IIC_VSHLi4D, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [4, 1, 1]>, + // + // Quad-register Integer Shift (4 cycle) + InstrItinData<IIC_VSHLi4Q, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [4, 1, 1]>, + // // Double-register Integer Binary (4 cycle) InstrItinData<IIC_VBINi4D, [InstrStage2<1, [FU_DRegsN], 0, Required>, // Extra 3 latency cycle since wbck is 6 cycles |
