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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:20:58 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:20:58 +0000 |
| commit | f64c7ca5c324de360d9747c2fb651cc2673ce200 (patch) | |
| tree | afd2570798d63c6874b499266624790e7972372a /llvm/lib/Target | |
| parent | 2ef0a12fa10f5e2cc9b1196259064e08f0eb9fc1 (diff) | |
| download | bcm5719-llvm-f64c7ca5c324de360d9747c2fb651cc2673ce200.tar.gz bcm5719-llvm-f64c7ca5c324de360d9747c2fb651cc2673ce200.zip | |
Add MAC stuff for A9
llvm-svn: 100660
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleV7.td | 60 |
1 files changed, 59 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleV7.td b/llvm/lib/Target/ARM/ARMScheduleV7.td index 7bd8811bf8c..39900a5d810 100644 --- a/llvm/lib/Target/ARM/ARMScheduleV7.td +++ b/llvm/lib/Target/ARM/ARMScheduleV7.td @@ -937,7 +937,65 @@ def CortexA9Itineraries : ProcessorItineraries<[ // Extra 3 latency cycle since wbck is 6 cycles InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>, - InstrStage<2, [FU_NPipe]>], [6, 3, 1]> + InstrStage<2, [FU_NPipe]>], [6, 3, 1]>, + + // + // Double-register Integer Multiply (.8, .16) + InstrItinData<IIC_VMULi16D, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [6, 2, 2]>, + // + // Quad-register Integer Multiply (.8, .16) + InstrItinData<IIC_VMULi16Q, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 7 cycles + InstrStage2<8, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<2, [FU_NPipe]>], [7, 2, 2]>, + + // + // Double-register Integer Multiply (.32) + InstrItinData<IIC_VMULi32D, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 7 cycles + InstrStage2<8, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<2, [FU_NPipe]>], [7, 2, 1]>, + // + // Quad-register Integer Multiply (.32) + InstrItinData<IIC_VMULi32Q, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 9 cycles + InstrStage2<10, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<4, [FU_NPipe]>], [9, 2, 1]>, + // + // Double-register Integer Multiply-Accumulate (.8, .16) + InstrItinData<IIC_VMACi16D, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [6, 3, 2, 2]>, + // + // Double-register Integer Multiply-Accumulate (.32) + InstrItinData<IIC_VMACi32D, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 7 cycles + InstrStage2<8, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<2, [FU_NPipe]>], [7, 3, 2, 1]>, + // + // Quad-register Integer Multiply-Accumulate (.8, .16) + InstrItinData<IIC_VMACi16Q, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 7 cycles + InstrStage2<8, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<2, [FU_NPipe]>], [7, 3, 2, 2]>, + // + // Quad-register Integer Multiply-Accumulate (.32) + InstrItinData<IIC_VMACi32Q, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 9 cycles + InstrStage2<8, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<4, [FU_NPipe]>], [9, 3, 2, 1]> ]>; |
