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* X86_32: Large Symbol+Offset relocations.Jim Grosbach2012-09-261-8/+40
| | | | | | | | | | If the offset is more than 24-bits, it won't fit in a scattered relocation offset field, so we fall back to using a non-scattered relocation. rdar://12358909 llvm-svn: 164724
* Add case clauses for returning dsp accumulator encoding values in functionAkira Hatanaka2012-09-261-2/+4
| | | | | | getMipsRegisterNumbering. llvm-svn: 164720
* Add DSP accumulator registers and register class. Remove hi/lo registers.Akira Hatanaka2012-09-261-33/+9
| | | | llvm-svn: 164719
* Delete member MipsFunctionInfo::OutArgFIRange and code that accesses it.Akira Hatanaka2012-09-263-31/+8
| | | | llvm-svn: 164718
* Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.James Molloy2012-09-261-2/+2
| | | | llvm-svn: 164685
* Add SARX/SHRX/SHLX code generation supportMichael Liao2012-09-262-0/+61
| | | | llvm-svn: 164675
* Add RORX code generation supportMichael Liao2012-09-262-0/+27
| | | | llvm-svn: 164674
* Add MULX code generation supportMichael Liao2012-09-262-27/+83
| | | | llvm-svn: 164673
* Remove hasNoAVX method. Can just invert hasAVX instead.Craig Topper2012-09-262-7/+6
| | | | llvm-svn: 164664
* Add 'lock' prefix output support in assembly printerMichael Liao2012-09-263-33/+38
| | | | | | | | - Instead of embedding 'lock' into each mnemonic of atomic instructions except 'xchg', we teach X86 assembly printer to output 'lock' prefix similar to or consistent with code emitter. llvm-svn: 164659
* Initialize boolean variables in MipsSubtarget's constructor.Akira Hatanaka2012-09-251-1/+2
| | | | llvm-svn: 164642
* blank line for test commitReed Kotler2012-09-251-0/+1
| | | | llvm-svn: 164640
* TargetLowering interface to set/get minimum block entries for jump tables.Sebastian Pop2012-09-251-0/+2
| | | | | | | | | | | | | | Provide interface in TargetLowering to set or get the minimum number of basic blocks whereby jump tables are generated for switch statements rather than an if sequence. getMinimumJumpTableEntries() defaults to 4. setMinimumJumpTableEntries() allows target configuration. This patch changes the default for the Hexagon architecture to 5 as it improves performance on some benchmarks. llvm-svn: 164628
* Add missing i64 max/min/umax/umin on 32-bit targetMichael Liao2012-09-253-0/+90
| | | | | | - Turn on atomic6432.ll and add specific test case as well llvm-svn: 164616
* ARM: Darwin BL/BLX relocations to out-of-range symbols.Jim Grosbach2012-09-251-1/+48
| | | | | | | | | | | When a BL/BLX references a symbol in the same translation unit that is out of range, use an external relocation. The linker will use this to generate a branch island rather than a direct reference, allowing the relocation to resolve correctly. rdar://12359919 llvm-svn: 164615
* Consistently specify the assembly variant to MatchInstructionImpl.Bob Wilson2012-09-251-4/+8
| | | | llvm-svn: 164611
* Fix an illegal tailcall opt where the callee returns a double via xmm while ↵Evan Cheng2012-09-252-1/+10
| | | | | | caller returns x86_fp80 via st0. rdar://12229511 llvm-svn: 164588
* ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'.Jim Grosbach2012-09-251-0/+14
| | | | | | rdar://9795790 llvm-svn: 164577
* Mark jump tables in code sections with DataRegion directives.Jim Grosbach2012-09-241-0/+5
| | | | | | | | | Even out-of-line jump tables can be in the code section, so mark them as data-regions for those targets which support the directives. rdar://12362871&12362974 llvm-svn: 164571
* Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier2012-09-244-37/+0
| | | | | | Also remove an unused argument. llvm-svn: 164567
* Specify MachinePointerInfo as refering to the argument value and offset of theRoman Divacky2012-09-241-3/+5
| | | | | | | store when handling byval arguments. Thus preventing reordering of the store with load with post-RA scheduler. llvm-svn: 164553
* Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier2012-09-244-16/+0
| | | | llvm-svn: 164548
* ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable]NAKAMURA Takumi2012-09-221-0/+2
| | | | llvm-svn: 164459
* Whitespace.NAKAMURA Takumi2012-09-221-2/+2
| | | | llvm-svn: 164458
* Fix edge cases of ARM shift operands in arith instructions.Tim Northover2012-09-221-38/+6
| | | | | | | | | As before with load instructions, oddities like "asr #32", "rrx" could be printed incorrectly. Patch by Chris Lidbury. llvm-svn: 164456
* Fix the handling of edge cases in ARM shifted operands.Tim Northover2012-09-224-8/+35
| | | | | | | | | This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. llvm-svn: 164455
* Fix 16-bit atomic inst encoding and keep pseudo-inst starting with '#'Michael Liao2012-09-221-14/+14
| | | | llvm-svn: 164453
* Fix typo in r164357Michael Liao2012-09-221-1/+1
| | | | llvm-svn: 164452
* MIPS DSP: Add immediate leaves.Akira Hatanaka2012-09-221-0/+20
| | | | llvm-svn: 164435
* MIPS DSP: Add predicates and instruction template.Akira Hatanaka2012-09-221-0/+25
| | | | llvm-svn: 164434
* Add MIPS DSP register classes. Set actions of DSP vector operations and overrideAkira Hatanaka2012-09-212-0/+49
| | | | | | TargetLowering's callback functions. llvm-svn: 164431
* SelectionDAG node enums for MIPS DSP nodes.Akira Hatanaka2012-09-212-0/+55
| | | | llvm-svn: 164430
* Add MIPS accumulator and DSP control registers.Akira Hatanaka2012-09-212-1/+45
| | | | llvm-svn: 164429
* Add flags and feature bits for mips dsp.Akira Hatanaka2012-09-212-0/+9
| | | | llvm-svn: 164428
* [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.Chad Rosier2012-09-214-0/+16
| | | | llvm-svn: 164420
* Add comment.Chad Rosier2012-09-211-1/+2
| | | | llvm-svn: 164415
* Add comment.Chad Rosier2012-09-211-1/+2
| | | | llvm-svn: 164414
* [fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier2012-09-211-0/+6
| | | | | | | non-aligned i32 loads/stores. rdar://12304911 llvm-svn: 164381
* Fix a typo in r164357Michael Liao2012-09-211-8/+8
| | | | llvm-svn: 164372
* Make the 'get*AlignmentFromAttr' functions into member functions within the ↵Bill Wendling2012-09-211-1/+1
| | | | | | Attributes class. Now with fix. llvm-svn: 164370
* Cortex-A9 latency fixes (w/ -schedmodel only).Andrew Trick2012-09-211-5/+5
| | | | | | Quick review against the manual revealed a few obvious mistakes. llvm-svn: 164361
* Add missing i8 max/min/umax/umin supportMichael Liao2012-09-211-9/+44
| | | | | | - Fix PR5145 and turn on test 8-bit atomic ops llvm-svn: 164358
* Revise td of X86 atomic instructionsMichael Liao2012-09-213-218/+209
| | | | | | | - Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. llvm-svn: 164357
* Mips16FrameLowering.cpp: Remove unused TII introduced in r164349. ↵NAKAMURA Takumi2012-09-211-1/+0
| | | | | | [-Wunused-variable] llvm-svn: 164354
* Properly save and restore RA and Mips16 callee save registers S0,S1Akira Hatanaka2012-09-213-6/+52
| | | | | | Patch by Reed Kotler. llvm-svn: 164349
* [fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier2012-09-211-0/+6
| | | | | | | non-halfword-aligned i16 loads/stores. rdar://12304911 llvm-svn: 164345
* Tidy up. Whitespace.Jim Grosbach2012-09-211-2/+2
| | | | llvm-svn: 164344
* Tidy up. Formatting.Jim Grosbach2012-09-211-1/+1
| | | | llvm-svn: 164343
* ARM: Use a dedicated intrinsic for vector bitwise select.Jim Grosbach2012-09-211-2/+29
| | | | | | | | | | | The expression based expansion too often results in IR level optimizations splitting the intermediate values into separate basic blocks, preventing the formation of the VBSL instruction as the code author intended. In particular, LICM would often hoist part of the computation out of a loop. rdar://11011471 llvm-svn: 164340
* Revert r164308 to fix buildbots.Bill Wendling2012-09-201-1/+1
| | | | llvm-svn: 164309
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