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| author | Chad Rosier <mcrosier@apple.com> | 2012-09-21 16:58:35 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2012-09-21 16:58:35 +0000 |
| commit | 8bf01fc663e6ea36f5bea482e9b9f143b9195468 (patch) | |
| tree | 27c4881a3c5475576439a954f48be7ba9ad216f6 /llvm/lib/Target | |
| parent | 7925fbbadbfd6af14b1c9f328ceb21bf1e13c529 (diff) | |
| download | bcm5719-llvm-8bf01fc663e6ea36f5bea482e9b9f143b9195468.tar.gz bcm5719-llvm-8bf01fc663e6ea36f5bea482e9b9f143b9195468.zip | |
[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for
non-aligned i32 loads/stores.
rdar://12304911
llvm-svn: 164381
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFastISel.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index af45ed7f473..f7f6b5dbb1c 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -1036,6 +1036,9 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, RC = &ARM::GPRRegClass; break; case MVT::i32: + if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) + return false; + if (isThumb2) { if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) Opc = ARM::t2LDRi8; @@ -1156,6 +1159,9 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, } break; case MVT::i32: + if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) + return false; + if (isThumb2) { if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) StrOpc = ARM::t2STRi8; |
