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| author | Chad Rosier <mcrosier@apple.com> | 2012-09-21 00:41:42 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2012-09-21 00:41:42 +0000 |
| commit | 2364f58326b696903b2dfb1f05cd7e92a7468639 (patch) | |
| tree | a9356cad01a4bbaf2a9ab906eef5bf796728d68c /llvm/lib/Target | |
| parent | e2baa97d60b04fa9518e370afd73502cf3ea142e (diff) | |
| download | bcm5719-llvm-2364f58326b696903b2dfb1f05cd7e92a7468639.tar.gz bcm5719-llvm-2364f58326b696903b2dfb1f05cd7e92a7468639.zip | |
[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for
non-halfword-aligned i16 loads/stores.
rdar://12304911
llvm-svn: 164345
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFastISel.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index 045d90424bd..af45ed7f473 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -1021,6 +1021,9 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, RC = &ARM::GPRRegClass; break; case MVT::i16: + if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) + return false; + if (isThumb2) { if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8; @@ -1139,6 +1142,9 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, } break; case MVT::i16: + if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) + return false; + if (isThumb2) { if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) StrOpc = ARM::t2STRHi8; |
