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* move this over to the dagAndrew Lenharth2005-12-052-10/+9
| | | | llvm-svn: 24609
* fix constant pool loadsAndrew Lenharth2005-12-051-1/+1
| | | | llvm-svn: 24607
* Several things:Chris Lattner2005-12-051-24/+32
| | | | | | | | | | | | | 1. Remove redundant type casts now that PR673 is implemented. 2. Implement the OUT*ir instructions correctly. The port number really *is* a 16-bit value, but the patterns should only match if the number is 0-255. Update the patterns so they now match. 3. Fix patterns for shifts to reflect that the shift amount is always an i8, not an i16 as they were believed to be before. This previous fib stopped working when we started knowing that CL has type i8. 4. Change use of i16i8imm in SH*ri patterns to all be imm. llvm-svn: 24599
* On some targets (e.g. X86), shift amounts are not the same as the valueChris Lattner2005-12-051-3/+6
| | | | | | being shifted. Don't assume they are. llvm-svn: 24598
* Add some explicit type casts so that tblgen knows the type of the ↵Chris Lattner2005-12-051-6/+6
| | | | | | shiftamount, which is not necessarily the same as the type being shifted. llvm-svn: 24595
* Add some explicit type casts so that tblgen knows the type of the shiftChris Lattner2005-12-051-5/+5
| | | | | | amount, which is not necessarily the same as the type being shifted. llvm-svn: 24594
* The basic fneg cases are already autogen'dChris Lattner2005-12-041-4/+2
| | | | llvm-svn: 24592
* Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgenChris Lattner2005-12-042-11/+12
| | | | | | improvements. llvm-svn: 24591
* Finish moving uncond br over to .td file, remove from .cpp file.Chris Lattner2005-12-042-4/+2
| | | | llvm-svn: 24590
* Define BR in the .td file now that Evan made tblgen smarter.Chris Lattner2005-12-042-5/+10
| | | | llvm-svn: 24589
* Added isel patterns for RET, JMP, and WRITEPORT.Evan Cheng2005-12-041-39/+53
| | | | llvm-svn: 24588
* * Added instruction property hasCtrlDep for those which r/w control-flowEvan Cheng2005-12-042-3/+27
| | | | | | | | | | | chains. * Added DAG node property SDNPHasChain for nodes which r/w control-flow chains. * Renamed SDTVT to SDTOther. * Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT. * Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT. llvm-svn: 24586
* Fix PR672 another way which should be more robustChris Lattner2005-12-041-16/+14
| | | | llvm-svn: 24585
* Fix test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll and PR672.Chris Lattner2005-12-031-0/+14
| | | | | | | | This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc turned on. Given a clean nightly tester run, we should be able to turn it on by default! llvm-svn: 24578
* add a noteChris Lattner2005-12-021-0/+6
| | | | llvm-svn: 24572
* IA64 doesn't support the LOCATION node, and for some reason the ISelPatternChris Lattner2005-12-011-0/+3
| | | | | | stuff isn't using ISelLowering.cpp llvm-svn: 24567
* Make sure these get added into the codegenmap when appropriateChris Lattner2005-12-011-4/+5
| | | | llvm-svn: 24566
* major think-oAndrew Lenharth2005-12-011-5/+10
| | | | llvm-svn: 24564
* Support multiple ValueTypes per RegisterClass, needed for upcoming vectorNate Begeman2005-12-019-34/+45
| | | | | | work. This change has no effect on generated code. llvm-svn: 24563
* Cosmetic change, better reflects actual valuesNate Begeman2005-12-011-6/+5
| | | | llvm-svn: 24562
* Fix a regression caused by a patch earlier todayChris Lattner2005-12-011-1/+2
| | | | llvm-svn: 24561
* Flags where I think I need them, quick, before the nightly tester startsAndrew Lenharth2005-12-011-23/+42
| | | | llvm-svn: 24560
* Proper support for shifts with register shift value.Evan Cheng2005-12-012-44/+24
| | | | llvm-svn: 24559
* Use a getCopyToReg() variant to generate a flaggy CopyToReg node.Evan Cheng2005-12-011-8/+2
| | | | llvm-svn: 24558
* SelectNodeTo now returns its result, we must pay attention to it.Chris Lattner2005-11-301-40/+29
| | | | llvm-svn: 24552
* Pay attn to the node returned by SelectNodeToChris Lattner2005-11-301-37/+28
| | | | llvm-svn: 24551
* SelectNodeTo now returns its result, we must pay attention to it.Chris Lattner2005-11-301-20/+18
| | | | llvm-svn: 24550
* SelectNodeTo now returns N. Use it instead of return N directly.Chris Lattner2005-11-301-108/+81
| | | | llvm-svn: 24549
* Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.llChris Lattner2005-11-301-2/+6
| | | | llvm-svn: 24547
* Fix a typo in my latest changeNate Begeman2005-11-301-2/+2
| | | | llvm-svn: 24542
* No longer track value types for asm printer operands, and remove them asNate Begeman2005-11-308-89/+92
| | | | | | | an argument to every operand printing function. Requires some slight tweaks to x86, the only user. llvm-svn: 24541
* remove redundant codeAndrew Lenharth2005-11-301-14/+2
| | | | llvm-svn: 24538
* Make typesafe that which isn't: FCMOVxxAndrew Lenharth2005-11-304-26/+52
| | | | llvm-svn: 24536
* FPSelect and more custom loweringAndrew Lenharth2005-11-305-25/+69
| | | | llvm-svn: 24535
* First chunk of actually generating vector code for packed types. TheseNate Begeman2005-11-301-11/+51
| | | | | | | | | | | | | | | | | | | | | | | changes allow us to generate the following code: _foo: li r2, 0 lvx v0, r2, r3 vaddfp v0, v0, v0 stvx v0, r2, r3 blr for this llvm: void %foo(<4 x float>* %a) { entry: %tmp1 = load <4 x float>* %a %tmp2 = add <4 x float> %tmp1, %tmp1 store <4 x float> %tmp2, <4 x float>* %a ret void } llvm-svn: 24534
* All sorts of stuff.Andrew Lenharth2005-11-307-32/+203
| | | | | | | | | | | | | Getting in on the custom lowering thing, yay evilness with fp setcc, yuck trivial int select, hmmm in memory args for functions, yay DIV and REM, always handy. They should be custom lowered though. Lots more stuff compiles now (go go single source!). Of course, none of it probably works, but that is what the nightly tester can find out :) llvm-svn: 24533
* Fix a bug in a recent patch that broke shiftsChris Lattner2005-11-301-3/+3
| | | | llvm-svn: 24526
* Added support to STORE and shifts to DAG to DAG isel.Evan Cheng2005-11-301-8/+88
| | | | llvm-svn: 24525
* Fixed a minor bug: - -offset != offset iff offset == MININTEvan Cheng2005-11-301-1/+1
| | | | llvm-svn: 24522
* Represent the encoding of the SPR instructions as they actually are, soNate Begeman2005-11-292-8/+18
| | | | | | | that we can use the correct SPR numbers in the InstrInfo.td file. This is necessary to support VRsave. llvm-svn: 24521
* Add more X86 ISel patterns.Evan Cheng2005-11-291-407/+463
| | | | llvm-svn: 24520
* Hook up one type, v4f32, to the VR RegisterClass for now.Nate Begeman2005-11-291-0/+6
| | | | llvm-svn: 24517
* Add the remainder of the AltiVec 4 x float instructions. FurtherNate Begeman2005-11-292-14/+61
| | | | | | | enhancements will be necessary to teach the code generator that since there is no fmul, it will have to do vmaddfp, adding +0.0. llvm-svn: 24516
* No targets support line number info yet.Chris Lattner2005-11-294-0/+12
| | | | llvm-svn: 24513
* Add the majority of the vector machien value types we expect to support,Nate Begeman2005-11-293-5/+11
| | | | | | | and make a few changes to the legalization machinery to support more than 16 types. llvm-svn: 24511
* Fixed a comment bug:Evan Cheng2005-11-291-1/+1
| | | | | | createPPCPatternInstructionSelector -> createPPCISelPattern llvm-svn: 24510
* refix typoChris Lattner2005-11-291-1/+1
| | | | llvm-svn: 24505
* don't say this is i128, because it isn't yet. Hopefully nate will changeChris Lattner2005-11-291-1/+1
| | | | | | | this to be something sane, but in the mean time it is unused, so safe to make something bogus. llvm-svn: 24504
* revert my change for the time being, which broke the buildChris Lattner2005-11-291-1/+1
| | | | llvm-svn: 24503
* fix a typo :)Chris Lattner2005-11-281-1/+1
| | | | llvm-svn: 24501
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