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| author | Chris Lattner <sabre@nondot.org> | 2005-12-05 02:34:29 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-12-05 02:34:29 +0000 |
| commit | c54cddd25b8e6a62164ea2b9f2461d1419100cd8 (patch) | |
| tree | 3a01f36c2d7ce21596a8fdc94ccc6a310f24f18d /llvm/lib/Target | |
| parent | f3322af5c6170b0649416d359ee22e7ea2e90531 (diff) | |
| download | bcm5719-llvm-c54cddd25b8e6a62164ea2b9f2461d1419100cd8.tar.gz bcm5719-llvm-c54cddd25b8e6a62164ea2b9f2461d1419100cd8.zip | |
Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.
llvm-svn: 24595
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/IA64/IA64InstrInfo.td | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/IA64/IA64InstrInfo.td b/llvm/lib/Target/IA64/IA64InstrInfo.td index fa5e9ce5222..4a349b0a9a9 100644 --- a/llvm/lib/Target/IA64/IA64InstrInfo.td +++ b/llvm/lib/Target/IA64/IA64InstrInfo.td @@ -156,31 +156,31 @@ def ZXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;", def MIX1L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "mix1.l $dst = $src1, $src2;;", [(set GR:$dst, (or (and GR:$src1, isMIX1Lable), - (and (srl GR:$src2, 8), isMIX1Lable)))]>; + (and (srl GR:$src2, (i64 8)), isMIX1Lable)))]>; def MIX2L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "mix2.l $dst = $src1, $src2;;", [(set GR:$dst, (or (and GR:$src1, isMIX2Lable), - (and (srl GR:$src2, 16), isMIX2Lable)))]>; + (and (srl GR:$src2, (i64 16)), isMIX2Lable)))]>; def MIX4L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "mix4.l $dst = $src1, $src2;;", [(set GR:$dst, (or (and GR:$src1, isMIX4Lable), - (and (srl GR:$src2, 32), isMIX4Lable)))]>; + (and (srl GR:$src2, (i64 32)), isMIX4Lable)))]>; def MIX1R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "mix1.r $dst = $src1, $src2;;", - [(set GR:$dst, (or (and (shl GR:$src1, 8), isMIX1Rable), + [(set GR:$dst, (or (and (shl GR:$src1, (i64 8)), isMIX1Rable), (and GR:$src2, isMIX1Rable)))]>; def MIX2R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "mix2.r $dst = $src1, $src2;;", - [(set GR:$dst, (or (and (shl GR:$src1, 16), isMIX2Rable), + [(set GR:$dst, (or (and (shl GR:$src1, (i64 16)), isMIX2Rable), (and GR:$src2, isMIX2Rable)))]>; def MIX4R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "mix4.r $dst = $src1, $src2;;", - [(set GR:$dst, (or (and (shl GR:$src1, 32), isMIX4Rable), + [(set GR:$dst, (or (and (shl GR:$src1, (i64 32)), isMIX4Rable), (and GR:$src2, isMIX4Rable)))]>; def GETFSIGD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, FP:$src), |
