Add the majority of the vector machien value types we expect to support,

and make a few changes to the legalization machinery to support more than
16 types.

llvm-svn: 24511

3 files changed, 11 insertions, 5 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 975dcbd31b3..c4ec815c17b 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -192,7 +192,7 @@ def F4RC : RegisterClass<"PPC", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7,
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def VRRC : RegisterClass<"PPC", f64/*FIXME*/, 128, [V0, V1, V2, V3, V4, V5, V6, V7, V8,
+def VRRC : RegisterClass<"PPC", v4f32, 128, [V0, V1, V2, V3, V4, V5, V6, V7, V8,
   V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23,
   V24, V25, V26, V27, V28, V29, V30, V31]>;
 
diff --git a/llvm/lib/Target/Target.td b/llvm/lib/Target/Target.td
index adb40af99c7..eeda4f9fe06 100644
--- a/llvm/lib/Target/Target.td
+++ b/llvm/lib/Target/Target.td
@@ -38,7 +38,13 @@ def f80    : ValueType<80 ,  9>;   // 80-bit floating point value
 def f128   : ValueType<128, 10>;   // 128-bit floating point value
 def FlagVT : ValueType<0  , 11>;   // Condition code or machine flag
 def isVoid : ValueType<0  , 12>;   // Produces no value
-def Vector : ValueType<0  , 13>;   // Abstract vector type
+def Vector : ValueType<0  , 13>;   // Abstract vector value
+def v16i8  : ValueType<128, 14>;   // 16 x i8  vector value
+def v8i16  : ValueType<128, 15>;   //  8 x i16 vector value
+def v4i32  : ValueType<128, 16>;   //  4 x i32 vector value
+def v2i64  : ValueType<128, 17>;   //  2 x i64 vector value
+def v4f32  : ValueType<128, 18>;   //  4 x f32 vector value
+def v2f64  : ValueType<128, 19>;   //  2 x f64 vector value
 
 //===----------------------------------------------------------------------===//
 // Register file description - These classes are used to fill in the target
diff --git a/llvm/lib/Target/TargetLowering.cpp b/llvm/lib/Target/TargetLowering.cpp
index 8570e649686..415084e2f1a 100644
--- a/llvm/lib/Target/TargetLowering.cpp
+++ b/llvm/lib/Target/TargetLowering.cpp
@@ -42,8 +42,8 @@ static void SetValueTypeAction(MVT::ValueType VT,
                                TargetLowering::LegalizeAction Action,
                                TargetLowering &TLI,
                                MVT::ValueType *TransformToType,
-                               unsigned &ValueTypeActions) {
-  ValueTypeActions |= Action << (VT*2);
+                               unsigned long long &ValueTypeActions) {
+  ValueTypeActions |= (unsigned long long)Action << (VT*2);
   if (Action == TargetLowering::Promote) {
     MVT::ValueType PromoteTo;
     if (VT == MVT::f32)
@@ -75,7 +75,7 @@ static void SetValueTypeAction(MVT::ValueType VT,
 /// computeRegisterProperties - Once all of the register classes are added,
 /// this allows us to compute derived properties we expose.
 void TargetLowering::computeRegisterProperties() {
-  assert(MVT::LAST_VALUETYPE <= 16 &&
+  assert(MVT::LAST_VALUETYPE <= 32 &&
          "Too many value types for ValueTypeActions to hold!");
 
   // Everything defaults to one.