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* Clean up language and grammar.Eric Christopher2014-05-201-1/+1
| | | | | | | Based on a patch by jfcaron3@gmail.com! PR19806 llvm-svn: 209216
* Temporarily revert: r209129 - [mips][mips64r6] Sorted *_ENC, *_DESC classes ↵Daniel Sanders2014-05-201-124/+117
| | | | | | | | | | | | and tests After discussion with Zoran, we have decided to temporarily revert this commit. It's causing some difficult to resolve conflicts and we are under time pressure to deliver an initial MIPS64r6 compiler. We will re-apply an equivalent patch once the time pressure has passed. llvm-svn: 209211
* TableGen: permit non-leaf ComplexPattern usesTim Northover2014-05-201-6/+8
| | | | | | | | | | | | | | | | | | This allows the results of a ComplexPattern check to be distributed to separate named Operands, instead of the current system where all results must apply (and match perfectly) with a single Operand. For example, if "some_addrmode" is a ComplexPattern producing two results, you can write: def : Pat<(load (some_addrmode GPR64:$base, imm:$offset)), (INST GPR64:$base, imm:$offset)>; This should allow neater instruction definitions in TableGen that don't put all possible aspects of addressing into a single operand, but are still usable with relatively simple C++ CodeGen idioms. llvm-svn: 209206
* Add parentheses to suppress the gcc warning '-Wparentheses'.Simon Atanasyan2014-05-201-2/+2
| | | | | | No functional changes. llvm-svn: 209203
* ARMEB: Additional test files for ARM fixupsChristian Pirker2014-05-201-1/+4
| | | | llvm-svn: 209200
* TableGen: convert InstAlias's Emit bit to an int.Tim Northover2014-05-202-68/+65
| | | | | | | | | | | | | When multiple aliases overlap, the correct string to print can often be determined purely by considering the InstAlias declarations in some particular order. This allows the user to specify that order manually when desired, without resorting to hacking around with the default lexicographical order on Record instantiation, which is error-prone and ugly. I was also mistaken about "add w2, w3, w4" being the same as "add w2, w3, w4, uxtw". That's only true if Rn is the stack pointer. llvm-svn: 209199
* [X86] Tune LEA usage for SilvermontAlexey Volkov2014-05-207-14/+102
| | | | | | | | | | | | | According to Intel Software Optimization Manual on Silvermont in some cases LEA is better to be replaced with ADD instructions: "The rule of thumb for ADDs and LEAs is that it is justified to use LEA with a valid index and/or displacement for non-destructive destination purposes (especially useful for stack offset cases), or to use a SCALE. Otherwise, ADD(s) are preferable." Differential Revision: http://reviews.llvm.org/D3826 llvm-svn: 209198
* [ARM64] Adds Cortex-A53 scheduling support for vector load/store post.Chad Rosier2014-05-194-60/+152
| | | | | | | Patch by Dave Estes<cestes@codeaurora.org>! PR19761 http://reviews.llvm.org/D3829 llvm-svn: 209176
* Remove unused method declarationMatt Arsenault2014-05-191-1/+0
| | | | llvm-svn: 209174
* [ConstantHoisting][X86] Change the cost model to never hoist constants for ↵Juergen Ributzka2014-05-191-2/+13
| | | | | | | | | | | | | | | types larger than i128. Currently the X86 backend doesn't support types larger than i128 very well. For example an i192 multiply will assert in codegen when the 2nd argument is a constant and the constant got hoisted. This fix changes the cost model to never hoist constants for types larger than i128. Once the codegen issues have been resolved, the cost model can be updated to allow also larger types. This is related to <rdar://problem/16954938> llvm-svn: 209162
* [X86] Add ISel patterns to improve the selection of TZCNT and LZCNT.Andrea Di Biagio2014-05-191-0/+81
| | | | | | | | | | Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
* Added more insertps optimizationsFilipe Cabecinhas2014-05-192-11/+72
| | | | | | | | | | | | | | | | | | | | Summary: When inserting an element that's coming from a vector load or a broadcast of a vector (or scalar) load, combine the load into the insertps instruction. Added PerformINSERTPSCombine for the case where we need to fix the load (load of a vector + insertps with a non-zero CountS). Added patterns for the broadcasts. Also added tests for SSE4.1, AVX, and AVX2. Reviewers: delena, nadav, craig.topper Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3581 llvm-svn: 209156
* reverting r209132Jyotsna Verma2014-05-192-121/+250
| | | | llvm-svn: 209139
* [ARM64] Split tbz/tbnz into W/X register variantBradley Smith2014-05-198-64/+144
| | | | llvm-svn: 209134
* Hexagon: Add encoding bits to the mpy instructions.Jyotsna Verma2014-05-192-250/+121
| | | | llvm-svn: 209132
* [mips][mips64r6] Sorted *_ENC, *_DESC classes and testsZoran Jovanovic2014-05-191-117/+124
| | | | | | Differential Revision: http://reviews.llvm.org/D3808 llvm-svn: 209129
* Resolving MSVC warnings about switch statements with a default label, but no ↵Aaron Ballman2014-05-192-11/+6
| | | | | | case labels. No functional changes intended. llvm-svn: 209126
* SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the ↵Benjamin Kramer2014-05-195-1/+24
| | | | | | | | | | bswap not. - On ARM/ARM64 we get a vrev because the shuffle matching code is really smart. We still unroll anything that's not v4i32 though. - On X86 we get a pshufb with SSSE3. Required more cleverness in isShuffleMaskLegal. - On PPC we get a vperm for v8i16 and v4i32. v2i64 is unrolled. llvm-svn: 209123
* ARM: make libcall setup more table drivenSaleem Abdulrasool2014-05-181-161/+100
| | | | | | | | | Rather than create a series of function calls to setup the library calls, create a table with the information and just use the table to drive the configuration of the library calls. This makes it easier to both inspect the list as well as to modify it. NFC. llvm-svn: 209089
* ARM: improve WoA ABI conformance for frame registerSaleem Abdulrasool2014-05-181-3/+7
| | | | | | | | | Windows on ARM uses R11 for the frame pointer even though the environment is a pure Thumb-2, thumb-only environment. Replicate this behaviour to improve Windows ABI compatibility. This register is used for fast stack walking, and thus is part of the Windows ABI. llvm-svn: 209085
* ARM: consolidate frame pointer register knowledgeSaleem Abdulrasool2014-05-181-3/+5
| | | | | | | | | | | Use the ARMBaseRegisterInfo to query the frame register. The base register info is aware of the frame register that is used for the frame pointer. Use that to determine the frame register rather than duplicating the knowledge. Although, the code path is slightly different in that it may return SP, that can only occur if the frame pointer has been omitted in the machine function, which is supposed to contain the desired value in that case. llvm-svn: 209084
* Target: remove old constructors for CallLoweringInfoSaleem Abdulrasool2014-05-1712-123/+97
| | | | | | | | | | This is mostly a mechanical change changing all the call sites to the newer chained-function construction pattern. This removes the horrible 15-parameter constructor for the CallLoweringInfo in favour of setting properties of the call via chained functions. No functional change beyond the removal of the old constructors are intended. llvm-svn: 209082
* Target: change member from reference to pointerSaleem Abdulrasool2014-05-174-6/+6
| | | | | | | | | This is a preliminary step to help ease the construction of CallLoweringInfo. Changing the construction to a chained function pattern requires that the parameter be nullable. However, rather than copying the vector, save a pointer rather than the reference to permit a late binding of the arguments. llvm-svn: 209080
* ARM: whitespaceSaleem Abdulrasool2014-05-171-3/+3
| | | | | | Remove some whitespace. NFC. llvm-svn: 209079
* Target: Replace getSection().empty() with hasSection()David Majnemer2014-05-171-1/+1
| | | | | | No functional change, just a small cleanup. llvm-svn: 209064
* ARM: use the proper target object format for WoASaleem Abdulrasool2014-05-171-1/+2
| | | | | | | | WoA uses COFF, not ELF. ARMISelLowering::createTLOF would previously return ELF for any non-MachO platform. This was a missed site when the original change for target format support for Windows on ARM was done. llvm-svn: 209057
* [x86] Fix a bad predicate I spotted by inspection -- pshufhw and pshuflwChandler Carruth2014-05-171-2/+2
| | | | | | | | | | were added in SSE2, no SSSE3. Found this while auditing all uses of SSSE3 in the X86 target. I don't actually expect this to make a significant difference on anything and I don't have any detailed test cases but I updated the existing test cases that already covered some of this code path. llvm-svn: 209056
* Use a sized enum for MachineOperandType. No functionality changePete Cooper2014-05-161-1/+1
| | | | llvm-svn: 209048
* Implemented special cases for PerformVSELECTCombine.Filipe Cabecinhas2014-05-161-0/+62
| | | | | | | | | | vselects with constant masks, after legalization, will get turned into specialized shuffle_vectors so they can be matched to blend+imm instructions. Fixed some tests. llvm-svn: 209044
* Lower vselects into X86ISD::BLENDI when appropriate.Filipe Cabecinhas2014-05-161-1/+83
| | | | | | | | | | | | | | | | LowerVSELECT will, if possible, generate a X86ISD::BLENDI DAG node if the condition is constant and we can emit that instruction, given the subtarget. This is not enough for all cases. An additional SELECTCombine optimization will be committed. Fixed tests that were expecting variable blends but where a blend+imm can be generated. Added test where we can't emit blend+immediate. Added avx2 blend+imm tests. llvm-svn: 209043
* Implemented LowerVSELECT to custom lower some instructions.Filipe Cabecinhas2014-05-162-16/+46
| | | | | | | | No functionality change intended. The types that previously were set to lower as Expand or Legal are doing the same thing with this lowering function. llvm-svn: 209042
* Delete getAliasedGlobal.Rafael Espindola2014-05-169-15/+11
| | | | llvm-svn: 209040
* R600/SI: Refactor the VOP3_32 tablegen classTom Stellard2014-05-166-34/+112
| | | | | | | | This will allow us to use a single MachineInstr to represent instructions which behave the same but have different encodings on some subtargets. llvm-svn: 209028
* R600/SI: Add a PredicateControl class for managing TableGen predicatesTom Stellard2014-05-163-28/+22
| | | | | | This was inspired by the PredicateControl class in the MIPS backend. llvm-svn: 209027
* R600/SI: Move tablegen patterns away from instruction defsTom Stellard2014-05-161-30/+31
| | | | llvm-svn: 209026
* R600/SI: Remove unused instructionTom Stellard2014-05-161-7/+0
| | | | llvm-svn: 209025
* R600/SI: Promote f32 SELECT to i32Tom Stellard2014-05-162-6/+2
| | | | llvm-svn: 209024
* R600/SI: Remove duplicate patternTom Stellard2014-05-161-5/+0
| | | | llvm-svn: 209023
* [ARM64] Increases the Sched Model accuracy for Cortex-A53.Chad Rosier2014-05-166-51/+228
| | | | | | | Patch by Dave Estes <cestes@codeaurora.org> http://reviews.llvm.org/D3769 llvm-svn: 209001
* [ARM64] Fix wrong comment in load/store optimization pass.Tilmann Scheller2014-05-161-1/+1
| | | | | | | | | | | | | | | | ldr x1, [x0, #64] add x0, x0, #64 -> ldr x1, [x0], #64 is not a valid transformation, the correct transformation (and what the code actually does) is: ldr x1, [x0, #64] add x0, x0, #64 -> ldr x1, [x0, #64]! llvm-svn: 208998
* Re-enable inline memcpy expansion for Thumb1.James Molloy2014-05-162-6/+5
| | | | | | Patch by Moritz Roth! llvm-svn: 208994
* Fix the Load/Store optimization pass to work with Thumb1.James Molloy2014-05-162-38/+238
| | | | | | Patch by Moritz Roth! llvm-svn: 208992
* Enable the Load/Store optimization pass for Thumb1 but make it return ↵James Molloy2014-05-162-8/+14
| | | | | | | | immediately for now. Patch by Moritz Roth! llvm-svn: 208991
* Fix a few comment typos and style issues.James Molloy2014-05-161-16/+17
| | | | | | Patch by Moritz Roth! llvm-svn: 208990
* [mips][mips64r6] Add SELEQZ and SELNEZ instructionsZoran Jovanovic2014-05-161-2/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D3743 llvm-svn: 208987
* [mips][mips64r6] Add Compact indexed jumps.Zoran Jovanovic2014-05-165-2/+81
| | | | | | Differential Revision: http://reviews.llvm.org/D3707 llvm-svn: 208981
* Revert "Implement global merge optimization for global variables."Rafael Espindola2014-05-164-36/+0
| | | | | | | | | | | | This reverts commit r208934. The patch depends on aliases to GEPs with non zero offsets. That is not supported and fairly broken. The good news is that GlobalAlias is being redesigned and will have support for offsets, so this patch should be a nice match for it. llvm-svn: 208978
* [mips][mips64r6] Add Compact zero-compare branch-and-link instructionsZoran Jovanovic2014-05-161-6/+37
| | | | | | Differential Revision: http://reviews.llvm.org/D3718 llvm-svn: 208977
* [mips][mips64r6] Add compact branch instructionsZoran Jovanovic2014-05-166-10/+236
| | | | | | Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
* [mips][mips64r6] Add LWPC and LWUPC instructionsZoran Jovanovic2014-05-162-4/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D3788 llvm-svn: 208971
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