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* Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and ↵Daniel Sanders2015-09-1593-424/+395
| | | | | | | | related. NFC. Eric has replied and has demanded the patch be reverted. llvm-svn: 247702
* [mips][microMIPS] Fix an issue with disassembling lwm32 instructionZoran Jovanovic2015-09-151-1/+1
| | | | | | | Fixed microMIPS disassembler crash on test case generated by llvm-mc-fuzzer. Differential Revision: http://reviews.llvm.org/D12881 llvm-svn: 247698
* [mips] Add support for branch-likely pseudo-instructionsZoran Jovanovic2015-09-154-15/+61
| | | | | | Differential Revision: http://reviews.llvm.org/D10537 llvm-svn: 247697
* [SystemZ] Fix assertion failure in tryBuildVectorShuffleUlrich Weigand2015-09-151-1/+1
| | | | | | | | | | | Under certain circumstances, tryBuildVectorShuffle would attempt to create a BUILD_VECTOR node with an invalid combination of types. This happened when one of the components of the original BUILD_VECTOR was itself a TRUNCATE node. That TRUNCATE was stripped off during intermediate processing to simplify code, but when adding the node back to the result vector, we still need it to get the type right. llvm-svn: 247694
* Re-commit r247683: Replace Triple with a new TargetTuple in MCTargetDesc/* ↵Daniel Sanders2015-09-1593-395/+424
| | | | | | | | | | | | | | | | | | | | | | | | | | | | and related. NFC. Summary: This is the first patch in the series to migrate Triple's (which are ambiguous) to TargetTuple's (which aren't). For the moment, TargetTuple simply passes all requests to the Triple object it holds. Once it has replaced Triple, it will start to implement the interface in a more suitable way. This change makes some changes to the public C++ API. In particular, InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer() now take TargetTuples instead of Triples. The other public C++ API's have been left as-is for the moment to reduce patch size. This commit also contains a trivial patch to clang to account for the C++ API change. Thanks go to Pavel Labath for fixing LLDB for me. Reviewers: rengolin Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10969 llvm-svn: 247692
* Revert r247684 - Replace Triple with a new TargetTuple ...Daniel Sanders2015-09-1593-424/+395
| | | | | | LLDB needs to be updated in the same commit. llvm-svn: 247686
* Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.Daniel Sanders2015-09-1593-395/+424
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the first patch in the series to migrate Triple's (which are ambiguous) to TargetTuple's (which aren't). For the moment, TargetTuple simply passes all requests to the Triple object it holds. Once it has replaced Triple, it will start to implement the interface in a more suitable way. This change makes some changes to the public C++ API. In particular, InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer() now take TargetTuples instead of Triples. The other public C++ API's have been left as-is for the moment to reduce patch size. This commit also contains a trivial patch to clang to account for the C++ API change. Reviewers: rengolin Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10969 llvm-svn: 247683
* Fix namespace indentation and missing blank lines before 'public:' in ↵Daniel Sanders2015-09-158-91/+103
| | | | | | | | | | *MCAsmInfo.h. NFC. This is to reduce noise in a following commit. Also fixes a couple missing spaces before the reference operator. llvm-svn: 247679
* [mips][microMIPS] Implement CACHEE and PREFE instructions for microMIPS32r6Zoran Jovanovic2015-09-153-1/+31
| | | | | | Differential Revision: http://reviews.llvm.org/D11632 llvm-svn: 247670
* [mips] Added support for various EVA ASE instructions.Daniel Sanders2015-09-159-14/+345
| | | | | | | | | | | | | | | | | | | | Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669
* [WebAssembly] Implement int64-to-int32 conversion.Dan Gohman2015-09-151-0/+3
| | | | llvm-svn: 247649
* Improve ISel using across lane min/max reductionJun Bum Lim2015-09-141-53/+190
| | | | | | | | | | | | | | | | | | | | In vectorized integer min/max reduction code, the final "reduce" step is sub-optimal. In AArch64, this change wll combine : %svn0 = vector_shuffle %0, undef<2,3,u,u> %smax0 = smax %0, svn0 %svn3 = vector_shuffle %smax0, undef<1,u,u,u> %sc = setcc %smax0, %svn3, gt %n0 = extract_vector_elt %sc, #0 %n1 = extract_vector_elt %smax0, #0 %n2 = extract_vector_elt $smax0, #1 %result = select %n0, %n1, n2 becomes : %1 = smaxv %0 %result = extract_vector_elt %1, 0 This change extends r246790. llvm-svn: 247575
* [mips] Unified the MipsMemSimm9GPRAsmOperand and MipsMemSimm9AsmOperand ↵Daniel Sanders2015-09-143-24/+10
| | | | | | | | | | | | | | | | | | | operands, NFC. Summary: These operands had the same purpose, however the MipsMemSimm9GPRAsmOperand operand was only for micromips32r6 and the MipsMemSimm9AsmOperand did not have a ParserMatchClass. Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12730 llvm-svn: 247573
* [ARM] Extract shifts out of multiply-by-constantJohn Brawn2015-09-141-19/+111
| | | | | | | | | | | | | | | Turning (op x (mul y k)) into (op x (lsl (mul y k>>n) n)) is beneficial when we can do the lsl as a shifted operand and the resulting multiply constant is simpler to generate. Do this by doing the transformation when trying to select a shifted operand, as that ensures that it actually turns out better (the alternative would be to do it in PreprocessISelDAG, but we don't know for sure there if extracting the shift would allow a shifted operand to be used). Differential Revision: http://reviews.llvm.org/D12196 llvm-svn: 247569
* [mips] Remove redundant nested-name-specifier. NFCSimon Atanasyan2015-09-141-25/+12
| | | | llvm-svn: 247547
* [mips] Save a copy of MipsABIInfo in the MipsTargetStreamer to escape a ↵Simon Atanasyan2015-09-141-3/+4
| | | | | | | | | | | | | dangling pointer The MipsTargetELFStreamer can receive ABI info from many sources. For example, from the MipsAsmParser instance. Lifetime of the MipsAsmParser can be shorter than MipsTargetELFStreamer's lifetime. In that case we get a dangling pointer to MipsABIInfo. Differential Revision: http://reviews.llvm.org/D12805 llvm-svn: 247546
* [X86][MMX] Added shuffle decodes for MMX/3DNow! shuffles.Simon Pilgrim2015-09-133-2/+77
| | | | | | | Added shuffle decodes for MMX PUNPCK + PSHUFW shuffles. Added shuffle decodes for 3DNow! PSWAPD shuffles. llvm-svn: 247526
* AVX-512: Fixed a bug in OR/XOR operations for 512-bit FP values on KNL.Elena Demikhovsky2015-09-131-2/+16
| | | | | | | | | | | KNL does not have VXORPS, VORPS for 512-bit values. I use integer VPXOR, VPOR that actually do the same. X86ISD::FXOR/FOR are generated as a result of FSUB combining. Differential Revision: http://reviews.llvm.org/D12753 llvm-svn: 247523
* [x86] enable machine combiner reassociations for 128-bit vector logical ↵Sanjay Patel2015-09-121-0/+6
| | | | | | | | | | integer insts (2nd try) The changes in: test/CodeGen/X86/machine-cp.ll are just due to scheduling differences after some logic instructions were reassociated. llvm-svn: 247516
* [X86] Renamed lowerVectorShuffleAsUnpack NFCI.Simon Pilgrim2015-09-121-9/+10
| | | | | | Renamed to lowerVectorShuffleAsPermuteAndUnpack to make it clear that it lowers to more than just a UNPCK instruction. llvm-svn: 247513
* [X86] Moved lowerVectorShuffleWithUNPCK earlier to make reuse easier. NFCI.Simon Pilgrim2015-09-121-63/+59
| | | | llvm-svn: 247511
* revert r247506; need to verify changes in existing testsSanjay Patel2015-09-121-6/+0
| | | | llvm-svn: 247507
* [x86] enable machine combiner reassociations for 128-bit vector logical ↵Sanjay Patel2015-09-121-0/+6
| | | | | | integer insts llvm-svn: 247506
* Fix typos.Bruce Mitchener2015-09-123-8/+8
| | | | | | | | | | Summary: This fixes a variety of typos in docs, code and headers. Subscribers: jholewinski, sanjoy, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D12626 llvm-svn: 247495
* Use function attribute "stackrealign" to decide whether stackAkira Hatanaka2015-09-111-1/+1
| | | | | | | | | | | | | | | | | realignment should be forced. With this commit, we can now force stack realignment when doing LTO and do so on a per-function basis. Also, add a new cl::opt option "stackrealign" to CommandFlags.h which is used to force stack realignment via llc's command line. Out-of-tree projects currently using -force-align-stack to force stack realignment should make changes to attach the attribute to the functions in the IR. Differential Revision: http://reviews.llvm.org/D11814 llvm-svn: 247450
* [CodeGen] Refactor TLI/AtomicExpand interface to make LLSC explicit.Ahmed Bougacha2015-09-118-23/+36
| | | | | | | | | | | | | | | We used to have this magic "hasLoadLinkedStoreConditional()" callback, which really meant two things: - expand cmpxchg (to ll/sc). - expand atomic loads using ll/sc (rather than cmpxchg). Remove it, and, instead, introduce explicit callbacks: - bool shouldExpandAtomicCmpXchgInIR(inst) - AtomicExpansionKind shouldExpandAtomicLoadInIR(inst) Differential Revision: http://reviews.llvm.org/D12557 llvm-svn: 247429
* [CodeGen] Rename AtomicRMWExpansionKind to AtomicExpansionKind.Ahmed Bougacha2015-09-117-19/+18
| | | | | | This lets us generalize its usage to the other atomic instructions. llvm-svn: 247428
* PPCFrameLowering::emitEpilogue(): Avoid manipulating MBBI on iterator end.NAKAMURA Takumi2015-09-111-1/+1
| | | | | | It caused crash in MachineInstr::hasPropertyInBundle() since r247237. llvm-svn: 247395
* Pass BranchProbability/BlockMass by value instead of const& as they are ↵Cong Hou2015-09-1010-28/+26
| | | | | | small. NFC. llvm-svn: 247357
* [WinEH] Push and pop EBP for 32-bit funcletsReid Kleckner2015-09-101-7/+10
| | | | | | | | The Win32 EH runtime caller does not preserve EBP, even though it does preserve the CSRs (EBX, ESI, EDI) for us. The result was that each finally funclet call would leave the frame pointer off by 12 bytes. llvm-svn: 247348
* AMDGPU: Simplify debug printingMatt Arsenault2015-09-103-13/+8
| | | | llvm-svn: 247345
* AMDGPU: Use StringRef valueMatt Arsenault2015-09-101-1/+1
| | | | llvm-svn: 247344
* [SPARC] Switch to the Machine Scheduler.James Y Knight2015-09-102-1/+6
| | | | | | | | | | | | | The (mostly-deprecated) SelectionDAG-based ILPListDAGScheduler scheduler was making poor scheduling decisions, causing high register pressure and extraneous register spills. Switching to the newer machine scheduler generates better code -- even without there being a machine model defined for SPARC yet. (Actually committing the test changes too, this time, unlike r247315) llvm-svn: 247343
* Revert "[SPARC] Switch to the Machine Scheduler."James Y Knight2015-09-102-6/+1
| | | | | | | | This reverts commit r247315. Accidentally omitted test changes; will resubmit full change shortly. llvm-svn: 247328
* [SPARC] Switch to the Machine Scheduler.James Y Knight2015-09-102-1/+6
| | | | | | | | | | | The (mostly-deprecated) SelectionDAG-based ILPListDAGScheduler scheduler was making poor scheduling decisions, causing high register pressure and extraneous register spills. Switching to the newer machine scheduler generates better code -- even without there being a machine model defined for SPARC yet. llvm-svn: 247315
* Re-commit r247216: "Fix Clang-tidy misc-use-override warnings, other minor ↵Hans Wennborg2015-09-101-45/+45
| | | | | | | | | fixes" Except the changes that defined virtual destructors as =default, because that ran into problems with GCC 4.7 and overriding methods that weren't noexcept. llvm-svn: 247298
* Fix an undefined behavior introduces in r247234Steven Wu2015-09-101-1/+1
| | | | llvm-svn: 247296
* AVX512: Implemented encoding and intrinsics forIgor Breger2015-09-101-52/+109
| | | | | | | | | vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11802 llvm-svn: 247276
* [ARM] Do not use vtrn for vectorshuffle if the order is reversedJames Molloy2015-09-101-4/+13
| | | | | | | | The tests in isVTRNMask and isVTRN_v_undef_Mask should also check that the elements of the upper and lower half of the vectorshuffle occur in the correct order when both halves are used. Without this test the code assumes that it is correct to use vector transpose (vtrn) for the masks <1, 1, 0, 0> and <1, 3, 0, 2>, among others, but the transpose actually incorrectly generates shuffles for <0, 0, 1, 1> and <0, 2, 1, 3> in this case. Patch by Jeroen Ketema! llvm-svn: 247254
* [ADT] Switch a bunch of places in LLVM that were doing single-characterChandler Carruth2015-09-104-6/+6
| | | | | | | splits to actually use the single character split routine which does less work, and in a debug build is *substantially* faster. llvm-svn: 247245
* Enable the shrink wrapping optimization for PPC64.Kit Barton2015-09-103-77/+89
| | | | | | | | | | | | | | The changes in this patch are as follows: 1. Modify the emitPrologue and emitEpilogue methods to work properly when the prologue and epilogue blocks are not the first/last blocks in the function 2. Fix a bug in PPCEarlyReturn optimization caused by an empty entry block in the function 3. Override the runShrinkWrap PredicateFtor (defined in TargetMachine) to check whether shrink wrapping should run: Shrink wrapping will run on PPC64 (Little Endian and Big Endian) unless -enable-shrink-wrap=false is specified on command line A new test case, ppc-shrink-wrapping.ll was created based on the existing shrink wrapping tests for x86, arm, and arm64. Phabricator review: http://reviews.llvm.org/D11817 llvm-svn: 247237
* [AArch64] Match FI+offset in STNP addressing mode.Ahmed Bougacha2015-09-102-0/+26
| | | | | | | | | | | | | | | First, we need to teach isFrameOffsetLegal about STNP. It already knew about the STP/LDP variants, but those were probably never exercised, because it's only the load/store optimizer that generates STP/LDP, and the only user of the method is frame lowering, which runs earlier. The STP/LDP cases were wrong: they didn't take into account the fact that they return two results, not one, so the immediate offset will be the 4th operand, not the 3rd. Follow-up to r247234. llvm-svn: 247236
* [AArch64] Match base+offset in STNP addressing mode.Ahmed Bougacha2015-09-101-0/+16
| | | | | | Followup to r247231. llvm-svn: 247234
* [AArch64] Support selecting STNP.Ahmed Bougacha2015-09-103-0/+78
| | | | | | | | | | | | | | | | | | We could go through the load/store optimizer and match STNP where we would have matched a nontemporal-annotated STP, but that's not reliable enough, as an opportunistic optimization. Insetad, we can guarantee emitting STNP, by matching them at ISel. Since there are no single-input nontemporal stores, we have to resort to some high-bits-extracting trickery to generate an STNP from a plain store. Also, we need to support another, LDP/STP-specific addressing mode, base + signed scaled 7-bit immediate offset. For now, only match the base. Let's make it smart separately. Part of PR24086. llvm-svn: 247231
* AMDGPU/SI: Fix more cases of losing exec operandsMatt Arsenault2015-09-103-16/+12
| | | | llvm-svn: 247230
* AMDGPU/SI: Fix creating v_mov_b32s without exec usesMatt Arsenault2015-09-101-2/+14
| | | | | | | This will be caught by existing tests with a verifier check to be added in a future commit. llvm-svn: 247229
* Revert r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes"Hans Wennborg2015-09-101-45/+45
| | | | | | | This caused build breakges, e.g. http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/24926 llvm-svn: 247226
* [CodeGen] Make x86 nontemporal store patfrags generic. NFC.Ahmed Bougacha2015-09-101-19/+0
| | | | | | To be used by other targets. llvm-svn: 247225
* [WinEH] Add codegen support for cleanuppad and cleanupretReid Kleckner2015-09-105-6/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | All of the complexity is in cleanupret, and it mostly follows the same codepaths as catchret, except it doesn't take a return value in RAX. This small example now compiles and executes successfully on win32: extern "C" int printf(const char *, ...) noexcept; struct Dtor { ~Dtor() { printf("~Dtor\n"); } }; void has_cleanup() { Dtor o; throw 42; } int main() { try { has_cleanup(); } catch (int) { printf("caught it\n"); } } Don't try to put the cleanup in the same function as the catch, or Bad Things will happen. llvm-svn: 247219
* Fix Clang-tidy misc-use-override warnings, other minor fixesHans Wennborg2015-09-101-45/+45
| | | | | | | | Patch by Eugene Zelenko! Differential Revision: http://reviews.llvm.org/D12740 llvm-svn: 247216
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