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| author | Sanjay Patel <spatel@rotateright.com> | 2015-09-12 14:58:04 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2015-09-12 14:58:04 +0000 |
| commit | 08755c7dbc5a038b79521bcf7ac52cbb26ccfd4c (patch) | |
| tree | 8fd04fe94141598f33802aa1fc25e2f7e8ec1b9d /llvm/lib/Target | |
| parent | 48ffca0f47ad02319e6a7d604ac2aa44fce89d72 (diff) | |
| download | bcm5719-llvm-08755c7dbc5a038b79521bcf7ac52cbb26ccfd4c.tar.gz bcm5719-llvm-08755c7dbc5a038b79521bcf7ac52cbb26ccfd4c.zip | |
[x86] enable machine combiner reassociations for 128-bit vector logical integer insts
llvm-svn: 247506
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 8b883162999..446d4bce155 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -6408,6 +6408,12 @@ static bool isAssociativeAndCommutative(const MachineInstr &Inst) { case X86::IMUL16rr: case X86::IMUL32rr: case X86::IMUL64rr: + case X86::PANDrr: + case X86::PORrr: + case X86::PXORrr: + case X86::VPANDrr: + case X86::VPORrr: + case X86::VPXORrr: // Normal min/max instructions are not commutative because of NaN and signed // zero semantics, but these are. Thus, there's no need to check for global // relaxed math; the instructions themselves have the properties we need. |
