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* Realign BLEND patterns to match the general style for patterns in .td file.Bruno Cardoso Lopes2011-09-121-45/+42
| | | | llvm-svn: 139526
* Fix 80-columnsBruno Cardoso Lopes2011-09-121-12/+16
| | | | llvm-svn: 139525
* Port more encoding tests to decoding tests, and correct an improper Thumb2 ↵Owen Anderson2011-09-122-0/+36
| | | | | | pre-indexed load decoding this uncovered. llvm-svn: 139522
* Associate a MemOperand with LDWCP nodes introduced during ISel.Richard Osborne2011-09-121-3/+8
| | | | | | This information is required if we want LDWCP to be hoisted out of loops. llvm-svn: 139495
* Mark LDWCP as having no side effects.Richard Osborne2011-09-121-1/+1
| | | | llvm-svn: 139494
* Format patterns, remove unused X86blend patternsNadav Rotem2011-09-122-27/+34
| | | | llvm-svn: 139491
* Fix disassembling of one of the register/register forms of ↵Craig Topper2011-09-111-0/+62
| | | | | | MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. llvm-svn: 139486
* Fix disassembling of reverse register/register forms of ↵Craig Topper2011-09-111-4/+13
| | | | | | ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. llvm-svn: 139485
* CR fixes per Bruno's request.Nadav Rotem2011-09-113-94/+48
| | | | | | | Undo the changes from r139285 which added custom lowering to vselect. Add tablegen lowering for vselect. llvm-svn: 139479
* r139454 activates an assert in a case where we were doing the right thing ↵Eli Friedman2011-09-101-1/+9
| | | | | | anyway. Make that explicit, and un-XFAIL the testcase. llvm-svn: 139458
* Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp andRichard Trieu2011-09-101-1/+1
| | | | | | | | | | | | lib/ExecutionEngine/MCJIT/MCJIT.cpp from: assert("error"); to: assert(0 && "error"); llvm-svn: 139456
* Fixed an assert from:Richard Trieu2011-09-101-1/+1
| | | | | | | | | | | | | | assert("not implemented for target shuffle node"); to: assert(0 && "not implemented for target shuffle node"); This causes a test failure in CodeGen/X86/palignr.ll which has been marked as XFAIL for the time being. Test failure filed at PR10901. llvm-svn: 139454
* Thumb2 parsing and encoding for MOV(immediate).Jim Grosbach2011-09-102-4/+58
| | | | | | | Some aliases for MOV(register) also to keep existing T1 tests happy when run in thumbv7 mode. llvm-svn: 139440
* LDM writeback is not allowed if Rn is in the target register list.Owen Anderson2011-09-091-0/+19
| | | | llvm-svn: 139432
* Fix an ambiguously nested if.Owen Anderson2011-09-091-2/+2
| | | | llvm-svn: 139431
* Fix buildbot breakage caused by r139415. I missed one instance of a ↵Owen Anderson2011-09-091-1/+5
| | | | | | manually create ARM::tB. llvm-svn: 139429
* Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.Owen Anderson2011-09-093-2/+27
| | | | llvm-svn: 139422
* O64 will not be supported.Akira Hatanaka2011-09-092-2/+1
| | | | llvm-svn: 139421
* Make F31 and D15 non-reserved registers.Akira Hatanaka2011-09-092-5/+1
| | | | llvm-svn: 139420
* Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson2011-09-099-23/+70
| | | | | | have a predicate operand, unlike conditional branches. llvm-svn: 139415
* Mips32 does not reserve even-numbered floating point registers.Akira Hatanaka2011-09-091-5/+0
| | | | llvm-svn: 139412
* Drop support for Mips1 and Mips2.Akira Hatanaka2011-09-099-87/+6
| | | | llvm-svn: 139405
* Implement vector-select support for avx256. Refactor the vblend ↵Nadav Rotem2011-09-094-30/+63
| | | | | | implementation to have tablegen match the instruction by the node type llvm-svn: 139400
* Thumb2 assembly parsing and encoding for MLA and MLS.Jim Grosbach2011-09-091-2/+2
| | | | llvm-svn: 139399
* Thumb2 assembly parsing and encoding for LDRSB.Jim Grosbach2011-09-091-1/+11
| | | | llvm-svn: 139389
* Drop support for Allegrex. Allegrex implements a variant of Mips2.Akira Hatanaka2011-09-092-23/+0
| | | | llvm-svn: 139383
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-098-40/+125
| | | | llvm-svn: 139381
* Fix handling of Intel syntax disassembling of movs and stos to stop being ↵Craig Topper2011-09-091-12/+12
| | | | | | blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875. llvm-svn: 139353
* Change default target architecture from Mips1 to Mips32r1 in preparation forAkira Hatanaka2011-09-092-2/+2
| | | | | | | | | removing support for Mips1 and Mips2. This change and the ones that follow have been discussed with and approved by Bruno. llvm-svn: 139344
* 80 columns.Akira Hatanaka2011-09-093-3/+3
| | | | llvm-svn: 139339
* All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.Owen Anderson2011-09-081-2/+3
| | | | llvm-svn: 139329
* Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.Owen Anderson2011-09-081-12/+21
| | | | llvm-svn: 139328
* Dix the 80-columns and remove unsupported v8i16 type from the list of legal ↵Nadav Rotem2011-09-081-9/+12
| | | | | | vselect types. llvm-svn: 139324
* Thumb2 assembly parsing and encoding for LDRD(immediate).Jim Grosbach2011-09-086-25/+226
| | | | | | Refactor operand handling for STRD as well. Tests for that forthcoming. llvm-svn: 139322
* Add a AVX version of a simple i64 -> f64 bitcast. This could beBruno Cardoso Lopes2011-09-081-7/+21
| | | | | | | triggered using llc with -O0, which wouldn't let it be folded and expose the lack of this pattern. llvm-svn: 139320
* * Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into aBruno Cardoso Lopes2011-09-082-643/+653
| | | | | | | | | | | | | | | | | | | | single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
* Add AVX versions of blend vector operations and fix some issues noticedBruno Cardoso Lopes2011-09-083-15/+22
| | | | | | | | | | | | in Nadav's r139285 and r139287 commits. 1) Rename vsel.ll to a more descriptive name 2) Change the order of BLEND operands to "Op1, Op2, Cond", this is necessary because PBLENDVB is already used in different places with this order, and it was being emitted in the wrong way for vselect 3) Add AVX patterns and tests for the same SSE41 instructions llvm-svn: 139305
* Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.Bruno Cardoso Lopes2011-09-081-4/+14
| | | | | | | Triggered using llc -O0. Also fix some SET0PS patterns to their AVX forms and test it on the testcase. llvm-svn: 139304
* Add X86-SSE4 codegen support for vector-select.Nadav Rotem2011-09-084-4/+51
| | | | llvm-svn: 139285
* Thumb2 assembly parsing and encoding for LDR post-indexed.Jim Grosbach2011-09-082-27/+27
| | | | | | | More cleanup of the general indexed addressing T2 instructions. Still more to do, especially for stores. llvm-svn: 139272
* Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.Jim Grosbach2011-09-083-59/+112
| | | | | | | Adjust encoding of writeback load/store instructions to better reflect the way the operand types are represented. llvm-svn: 139270
* Remove the "common" set of instructions shared between ARM and Thumb2 modes. ↵Owen Anderson2011-09-082-20/+0
| | | | | | This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. llvm-svn: 139268
* Thumb2 assembly parsing and encoding for LDRBT.Jim Grosbach2011-09-072-13/+30
| | | | llvm-svn: 139267
* Thumb2 assembly parsing and encoding for LDR(register).Jim Grosbach2011-09-072-1/+25
| | | | llvm-svn: 139264
* Add two notes for correlated-expression optimizations.Benjamin Kramer2011-09-071-0/+10
| | | | llvm-svn: 139263
* Thumb2 assembly parsing and encoding for LDRB(immediate).Jim Grosbach2011-09-071-3/+7
| | | | llvm-svn: 139258
* Create Thumb2 versions of STC/LDC, and reenable the relevant tests.Owen Anderson2011-09-072-0/+132
| | | | llvm-svn: 139256
* Thumb2 parsing and encoding for LDR(immediate).Jim Grosbach2011-09-072-42/+96
| | | | | | | | | The immediate offset of the non-writeback i8 form (encoding T4) allows negative offsets only. The positive offset form of the encoding is the LDRT instruction. Immediate offsets in the range [0,255] use encoding T3 instead. llvm-svn: 139254
* Thumb2 parsing and encoding for LDMDB.Jim Grosbach2011-09-071-0/+1
| | | | llvm-svn: 139251
* Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds ↵James Molloy2011-09-071-16/+23
| | | | | | predicate checking to the Disassembler. llvm-svn: 139250
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