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* Fix up a misleading format warning.Eric Christopher2018-05-161-1/+1
* [MachineOutliner] Don't save/restore LR for tail calls.Eli Friedman2018-05-161-3/+4
* [X86] Fix typo in instregex for CVTSI642SDrrSimon Pilgrim2018-05-161-1/+1
* [X86][AVX512DQ] Use packed instructions for scalar FP<->i64 conversions on 32...Craig Topper2018-05-161-8/+62
* [AMDGPU] Change llvm.debugtrap to be a debug breakpoint that can resume execu...Tony Tye2018-05-162-34/+34
* [AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.Sander de Smalen2018-05-162-11/+42
* [AArch64] Gangup loads and stores for pairing.Sirish Pande2018-05-161-0/+2
* [AArch64][SVE] Asm: Support for gather PRF prefetch instructionsSander de Smalen2018-05-162-0/+159
* [mips] Simplify some of the predicate scopes for (negative) multiply add/sub ...Simon Dardis2018-05-161-23/+20
* [mips] Join existing scopes for DecoderNamespace (NFCI)Simon Dardis2018-05-161-6/+3
* AMDGPU: Custom lower v4i16/v4f16 vector operationsMatt Arsenault2018-05-164-19/+124
* [X86] Split WriteCvtI2F/WriteCvtF2I into I<->F32 and I<->F64 scheduler classesSimon Pilgrim2018-05-1614-359/+338
* [GlobalISel][IRTranslator] Split aggregates during IR translation.Amara Emerson2018-05-162-1/+9
* [mips] Add support for isBranchOffsetInRange and use it for MipsLongBranchSimon Dardis2018-05-164-14/+205
* [AArch64] Support "S" inline assembler constraintPeter Smith2018-05-162-1/+25
* [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) l...Sander de Smalen2018-05-162-0/+36
* [AArch64][SVE] Asm: Support for contiguous PRF prefetch instructions.Sander de Smalen2018-05-164-2/+77
* Remove unused variable introduced in r332336Mikael Holmen2018-05-161-1/+1
* ARM: Remove unnecessary argument. NFCI.Peter Collingbourne2018-05-162-6/+3
* ARM: Deduplicate code and remove unnecessary declaration. NFCI.Peter Collingbourne2018-05-163-47/+11
* [AMDGPU] Fix handling of void types in isLegalAddressingModeStanislav Mekhanoshin2018-05-151-1/+1
* [AArch64] Improve single vector lane unscaled storesEvandro Menezes2018-05-151-0/+16
* Nios2: Unbreak build.Peter Collingbourne2018-05-152-5/+6
* [x86][eflags] Fix PR37431 by teaching the EFLAGS copy lowering toChandler Carruth2018-05-151-3/+142
* AMDGPU: Fix v_dot{4, 8}* instruction encodingKonstantin Zhuravlyov2018-05-152-8/+13
* AMDGPU/GlobalISel: Implement select() for G_FCONSTANTTom Stellard2018-05-151-15/+47
* AMDGPU: Add disasm tests for deep learning instructions + fix v_fmac_f32 disasmKonstantin Zhuravlyov2018-05-151-1/+2
* [X86] Split WriteCvtF2F into F32->F64 and F64->F32 scheduler classesSimon Pilgrim2018-05-1512-136/+181
* [Hexagon] Remove unused function from subtargetKrzysztof Parzyszek2018-05-151-8/+0
* [Hexagon] Remove unused flag from subtarget and (non)corresponding testKrzysztof Parzyszek2018-05-153-8/+0
* [mips] Mark select instructions correctlySimon Dardis2018-05-153-151/+192
* [X86] Split off F16C WriteCvtPH2PS/WriteCvtPS2PH scheduler classesSimon Pilgrim2018-05-1512-139/+121
* [mips] Fix formatting of floating point conversion patternsSimon Dardis2018-05-151-8/+8
* [mips] Add disassembly support for comparison instructionsSimon Dardis2018-05-151-4/+6
* [mips] Fix predicates of mfc1, mtc1 instructionsSimon Dardis2018-05-152-28/+22
* [X86] Improve unsigned saturation downconvert detection.Artur Gainullin2018-05-151-19/+52
* [RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxa...Shiva Chen2018-05-153-0/+14
* [ARM] Back up R4 and LR if calling the stack probe functionMartin Storsjo2018-05-141-0/+11
* [Hexagon] Add a target feature to control using small data sectionKrzysztof Parzyszek2018-05-144-16/+20
* [Hexagon] Add a target feature for generating new-value storesKrzysztof Parzyszek2018-05-143-6/+18
* [Hexagon] Add a target feature for memop generationKrzysztof Parzyszek2018-05-144-31/+32
* [X86] Add NT load/store scheduler classesSimon Pilgrim2018-05-1413-84/+148
* [X86] Remove and autoupgrade avx512.vbroadcast.ss/avx512.vbroadcast.sd intrin...Craig Topper2018-05-141-5/+0
* [X86][BtVer2] Fix MMX/YMM integer vector nt store schedulesSimon Pilgrim2018-05-141-2/+8
* [Hexagon] Avoid predicate copies to integer registers from store-lockedKrzysztof Parzyszek2018-05-141-0/+15
* [mips] Fix the predicates of round, ceiling, floor and trunc.Simon Dardis2018-05-142-38/+36
* [NFC] [Power] Fix instruction format for xsrqpiZaara Syeda2018-05-142-1/+22
* [AArch64] Improve single vector lane storesEvandro Menezes2018-05-141-20/+57
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-14184-2642/+2719
* [AArch64][SVE] Extend parsing of Prefetch operation for SVE.Sander de Smalen2018-05-147-10/+99
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