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* [mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, MADD...Zoran Jovanovic2015-09-053-4/+159
* [PowerPC] Fix and(or(x, c1), c2) -> rlwimi generationHal Finkel2015-09-051-3/+15
* [PowerPC] Enable interleaved-access vectorizationHal Finkel2015-09-042-1/+43
* [PowerPC] Always use aggressive interleaving on the A2Hal Finkel2015-09-031-0/+7
* [PowerPC] Try harder to find a base+offset when looking for consecutive accessesHal Finkel2015-09-031-7/+23
* [PowerPC] Include the permutation cost for unaligned vector loadsHal Finkel2015-09-031-8/+12
* [PowerPC] Compute the MMO offset for an unaligned load with signed arithmeticHal Finkel2015-09-031-1/+2
* [AArch64] Improve ISel using across lane addition reduction.Chad Rosier2015-09-031-0/+99
* Sink COFF.h MC include into .cpp filesReid Kleckner2015-09-031-0/+1
* Revert "[AArch64] Improve load/store optimizer to handle LDUR + LDR."Chad Rosier2015-09-031-77/+21
* [x86] enable machine combiner reassociations for scalar 'xor' instsSanjay Patel2015-09-031-0/+4
* check for fastness before merging in DAGCombiner::MergeConsecutiveStores() Sanjay Patel2015-09-031-1/+4
* [AArch64] Improve load/store optimizer to handle LDUR + LDR.Chad Rosier2015-09-031-21/+77
* [AArch64] Reuse MayLoad. NFC.Chad Rosier2015-09-031-1/+1
* [mips] Added support for the div, divu, ddiv and ddivu macros which use traps...Daniel Sanders2015-09-035-1/+182
* AVX512: Implemented encoding and intrinsics for vplzcntq, vplzcntd, vpconflic...Igor Breger2015-09-035-117/+54
* [X86] Require 32-byte alignment for 32-byte VMOVNTs.Ahmed Bougacha2015-09-021-2/+4
* [X86] Cleanup nontemporal fragments. NFCI.Ahmed Bougacha2015-09-021-15/+6
* [PowerPC] Cleanup cost model for unaligned vector loads/storesHal Finkel2015-09-021-22/+37
* [AArch64] More consistently separate asm opc and operands with '\t'.Ahmed Bougacha2015-09-021-30/+30
* [AArch64] Consistently separate asm opc and operands with '\t'.Ahmed Bougacha2015-09-021-17/+17
* [PowerPC] Don't always consider P8Altivec-only masks in LowerVECTOR_SHUFFLEHal Finkel2015-09-021-6/+8
* [x86] fix allowsMisalignedMemoryAccesses() for 8-byte and smaller accessesSanjay Patel2015-09-021-5/+13
* [X86][AVX512VLBW] add support in byte shift and SADAsaf Badouh2015-09-024-7/+83
* AVX512: Implemented encoding and intrinsics for VGETMANTPD/S , VGETMANTSD/S i...Igor Breger2015-09-025-17/+63
* AVX512: Implemented encoding and intrinsics for vshufps/d.Igor Breger2015-09-023-44/+36
* AVX-512: store <4 x i1> and <2 x i1> values in memoryElena Demikhovsky2015-09-021-0/+5
* [CodeGen] Fix FREM on 32-bit MSVC on x86Vedant Kumar2015-09-021-1/+11
* [ARM] Don't abort on variable-idx extractelt in ReconstructShuffle.Ahmed Bougacha2015-09-011-0/+4
* rename "slow-unaligned-mem-under-32" to slow-unaligned-mem-16" (NFCI)Sanjay Patel2015-09-015-53/+59
* [AArch64] Lower READCYCLECOUNTER using MRS PMCCTNR_EL0.Ahmed Bougacha2015-09-015-6/+25
* AVX512: Implemented intrinsics for valign.Igor Breger2015-09-011-0/+8
* [AArch64] Turn on by default interleaved access vectorizationSilviu Baranga2015-09-011-0/+2
* [ARM] Turn on by default interleaved access vectorizationSilviu Baranga2015-09-011-0/+2
* AMDGPU: Fix adding redundant implicit operandsMatt Arsenault2015-09-011-11/+7
* WebAssembly: generate load/storeJF Bastien2015-08-313-49/+113
* [x86] enable machine combiner reassociations for scalar 'or' instsSanjay Patel2015-08-311-0/+4
* [EH] Handle non-Function personalities like unknown personalitiesReid Kleckner2015-08-311-7/+7
* [AArch64][CollectLOH] Remove an invalid assertion and add a test case exposin...Quentin Colombet2015-08-311-3/+11
* AArch64: Fix loads to lower NEON vector lanes using GPR registersMatthias Braun2015-08-311-1/+4
* X86: Fix FastISel SSESelect register classMatthias Braun2015-08-311-3/+9
* AVX512: ktest implemantationIgor Breger2015-08-314-14/+16
* AVX512: Implemented encoding and intrinsics for vdbpsadbwIgor Breger2015-08-315-1/+15
* AVX512: kadd implementationIgor Breger2015-08-311-2/+4
* AVX512: Implemented encoding and intrinsics for vpalignrIgor Breger2015-08-314-34/+92
* [PowerPC] Fixup SELECT_CC (and SETCC) patterns with i1 comparison operandsHal Finkel2015-08-304-5/+168
* [MIR Serialization] static -> static const in getSerializable*MachineOperandT...Hal Finkel2015-08-303-5/+5
* [PowerPC/MIR Serialization] Target flags serialization supportHal Finkel2015-08-302-0/+41
* [PowerPC] Don't assume ADDISdtprelHA's source is r3Hal Finkel2015-08-301-5/+5
* [Triple] Stop abusing a class to have only static methods and just useChandler Carruth2015-08-303-13/+13
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