summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.Chad Rosier2012-09-214-0/+16
| | | | llvm-svn: 164420
* Add comment.Chad Rosier2012-09-211-1/+2
| | | | llvm-svn: 164415
* Add comment.Chad Rosier2012-09-211-1/+2
| | | | llvm-svn: 164414
* [fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier2012-09-211-0/+6
| | | | | | | non-aligned i32 loads/stores. rdar://12304911 llvm-svn: 164381
* Fix a typo in r164357Michael Liao2012-09-211-8/+8
| | | | llvm-svn: 164372
* Make the 'get*AlignmentFromAttr' functions into member functions within the ↵Bill Wendling2012-09-211-1/+1
| | | | | | Attributes class. Now with fix. llvm-svn: 164370
* Cortex-A9 latency fixes (w/ -schedmodel only).Andrew Trick2012-09-211-5/+5
| | | | | | Quick review against the manual revealed a few obvious mistakes. llvm-svn: 164361
* Add missing i8 max/min/umax/umin supportMichael Liao2012-09-211-9/+44
| | | | | | - Fix PR5145 and turn on test 8-bit atomic ops llvm-svn: 164358
* Revise td of X86 atomic instructionsMichael Liao2012-09-213-218/+209
| | | | | | | - Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. llvm-svn: 164357
* Mips16FrameLowering.cpp: Remove unused TII introduced in r164349. ↵NAKAMURA Takumi2012-09-211-1/+0
| | | | | | [-Wunused-variable] llvm-svn: 164354
* Properly save and restore RA and Mips16 callee save registers S0,S1Akira Hatanaka2012-09-213-6/+52
| | | | | | Patch by Reed Kotler. llvm-svn: 164349
* [fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier2012-09-211-0/+6
| | | | | | | non-halfword-aligned i16 loads/stores. rdar://12304911 llvm-svn: 164345
* Tidy up. Whitespace.Jim Grosbach2012-09-211-2/+2
| | | | llvm-svn: 164344
* Tidy up. Formatting.Jim Grosbach2012-09-211-1/+1
| | | | llvm-svn: 164343
* ARM: Use a dedicated intrinsic for vector bitwise select.Jim Grosbach2012-09-211-2/+29
| | | | | | | | | | | The expression based expansion too often results in IR level optimizations splitting the intermediate values into separate basic blocks, preventing the formation of the VBSL instruction as the code author intended. In particular, LICM would often hoist part of the computation out of a loop. rdar://11011471 llvm-svn: 164340
* Revert r164308 to fix buildbots.Bill Wendling2012-09-201-1/+1
| | | | llvm-svn: 164309
* Make the 'get*AlignmentFromAttr' functions into member functions within the ↵Bill Wendling2012-09-201-1/+1
| | | | | | Attributes class. llvm-svn: 164308
* Change enum type in a static table to uint8_t instead. Saves about 700 ↵Craig Topper2012-09-201-6/+6
| | | | | | hundred bytes of static data. Change unsigned char in same table to uint8_t for explicitness. llvm-svn: 164285
* Re-work X86 code generation of atomic ops with spin-loopMichael Liao2012-09-205-540/+508
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Rewrite/merge pseudo-atomic instruction emitters to address the following issue: * Reduce one unnecessary load in spin-loop previously the spin-loop looks like thisMBB: newMBB: ld t1 = [bitinstr.addr] op t2 = t1, [bitinstr.val] not t3 = t2 (if Invert) mov EAX = t1 lcs dest = [bitinstr.addr], t3 [EAX is implicit] bz newMBB fallthrough -->nextMBB the 'ld' at the beginning of newMBB should be lift out of the loop as lcs (or CMPXCHG on x86) will load the current memory value into EAX. This loop is refined as: thisMBB: EAX = LOAD [MI.addr] mainMBB: t1 = OP [MI.val], EAX LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined] JNE mainMBB sinkMBB: * Remove immopc as, so far, all pseudo-atomic instructions has all-register form only, there is no immedidate operand. * Remove unnecessary attributes/modifiers in pseudo-atomic instruction td * Fix issues in PR13458 - Add comprehensive tests on atomic ops on various data types. NOTE: Some of them are turned off due to missing functionality. - Revise tests due to the new spin-loop generated. llvm-svn: 164281
* Unify the logic in SelectAtomicLoadAdd and SelectAtomicLoadArithMichael Liao2012-09-191-176/+140
| | | | | | | | | | | - Merge the processing of LOAD_ADD with other atomic load-arith operations - Separate the logic getting target constant for atomic-load-op and add an optimization for atomic-load-add on i16 with negative value - Optimize a minor case for atomic-fetch-add i16 with negative operand. Test case is revised. llvm-svn: 164243
* Small structs for PPC64 SVR4 must be passed right-justified in registers.Bill Schmidt2012-09-192-61/+143
| | | | | | | | | | | | | | | lib/Target/PowerPC/PPCISelLowering.{h,cpp} Rename LowerFormalArguments_Darwin to LowerFormalArguments_Darwin_Or_64SVR4. Rename LowerFormalArguments_SVR4 to LowerFormalArguments_32SVR4. Receive small structs right-justified in LowerFormalArguments_Darwin_Or_64SVR4. Rename LowerCall_Darwin to LowerCall_Darwin_Or_64SVR4. Rename LowerCall_SVR4 to LowerCall_32SVR4. Pass small structs right-justified in LowerCall_Darwin_Or_64SVR4. test/CodeGen/PowerPC/structsinregs.ll New test. llvm-svn: 164228
* Remove code for setting the VEX L-bit as a function of operand size from the ↵Craig Topper2012-09-193-22/+2
| | | | | | code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. llvm-svn: 164204
* Add explicit VEX_L tags to all 256-bit instructions. This will allow us to ↵Craig Topper2012-09-193-240/+254
| | | | | | remove code from the code emitters that examined operands to set the L-bit. llvm-svn: 164202
* MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648Evan Cheng2012-09-181-2/+4
| | | | llvm-svn: 164169
* Fix the isLocalCall() by checking for linker weakness as well.Roman Divacky2012-09-181-1/+2
| | | | llvm-svn: 164155
* Revert r164051.Akira Hatanaka2012-09-181-4/+0
| | | | llvm-svn: 164150
* Avoid symbol name clash when filling TOC.Roman Divacky2012-09-181-3/+8
| | | | | | Patch by Adhemerval Zanella. llvm-svn: 164141
* On PPC64 emit the environment pointer. Patch by Adhemerval Zanella.Roman Divacky2012-09-181-0/+2
| | | | llvm-svn: 164139
* Optimize local func calls to not emit nop for TOC restoration.Roman Divacky2012-09-181-2/+10
| | | | | | Patch by Adhemerval Zanella. llvm-svn: 164138
* When creating MCAsmBackend pass the CPU string as well. In X86AsmBackendRoman Divacky2012-09-1810-40/+58
| | | | | | | | | store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. llvm-svn: 164132
* More domain conversion; convert VFP VMOVS to NEON instructions in more cases ↵James Molloy2012-09-181-13/+56
| | | | | | - when we may clobber the other S-lane by converting an S to a D instruction, make an effort to work out if the S lane is clobberable or not. llvm-svn: 164114
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-181-1/+2
| | | | | | model. llvm-svn: 164092
* Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byteEvan Cheng2012-09-182-5/+42
| | | | | | | | | aligned address. Based on patch by David Peixotto. Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment hints. rdar://12090772, rdar://12238782 llvm-svn: 164089
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-171-2/+1
| | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-171-1/+2
| | | | | | model. llvm-svn: 164061
* Add some cases to x86 OptimizeCompare to handle DEC and INC, too.Jan Wen Voung2012-09-171-4/+14
| | | | | | While we are setting the earlier def to true, also make it live. llvm-svn: 164056
* Make sure there is enough room for RA. getStackSize needs to be cleaned up butAkira Hatanaka2012-09-171-0/+4
| | | | | | | | we will do that when we implement the full save/restore. Patch by Reed Kotler. llvm-svn: 164051
* LLVM_ATTRIBUTE_USED forces emission of a function. To silence unused ↵Benjamin Kramer2012-09-171-2/+2
| | | | | | function warnings use LLVM_ATTRIBUTE_UNUSED. llvm-svn: 164036
* Removed the VMLxForwarding feature for the Cortex-A15 target.Silviu Baranga2012-09-171-2/+1
| | | | llvm-svn: 164030
* Change unsigned to uint32_t to match base class declaration and other targets.Craig Topper2012-09-162-2/+2
| | | | llvm-svn: 164001
* The PMOVZXWD family of functions had patterns extends narrow vector types to ↵Nadav Rotem2012-09-161-0/+24
| | | | | | | | | | | wide vector types. It had patterns for zext-loading and extending. This commit adds patterns for loading a wide type, performing a bitcast, and extending. This is an odd pattern, but it is commonly used when writing code with intrinsics. rdar://11897677 llvm-svn: 163995
* Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.Craig Topper2012-09-154-9/+9
| | | | llvm-svn: 163974
* Remove unused private fields to silence -Wunused-private-field.Craig Topper2012-09-151-9/+6
| | | | llvm-svn: 163973
* X86: Emitting x87 fsin/fcos for sinf/cosf is not safe without unsafe fp math.Benjamin Kramer2012-09-151-0/+2
| | | | | | This was only an issue if sse is disabled. llvm-svn: 163967
* Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td andAkira Hatanaka2012-09-156-146/+52
| | | | | | | | | | use load/store fragments defined in TargetSelectionDAG.td in place of them. Unaligned loads/stores are either expanded or lowered to target-specific nodes, so instruction selection should see only aligned load/store nodes. No changes in functionality. llvm-svn: 163960
* Handled unaligned load/stores properly in Mips16 Akira Hatanaka2012-09-151-2/+7
| | | | | | Patch by Reed Kotler. llvm-svn: 163956
* Implement getNumLDMAddresses and expose through ARMBaseInstrInfo.Andrew Trick2012-09-142-0/+34
| | | | llvm-svn: 163922
* Cortex-A9 instruction-level scheduling machine model.Andrew Trick2012-09-141-3/+594
| | | | | | | | | | | | | | | | | | | | This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
* DAG post-process for Hexagon MI schedulerSergei Larin2012-09-142-0/+34
| | | | | | | | This patch introduces a possibility for Hexagon MI scheduler to perform some target specific post- processing on the scheduling DAG prior to scheduling. llvm-svn: 163903
* Fix Doxygen issues:Dmitri Gribenko2012-09-145-20/+20
| | | | | | | | | | * wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph); * use \param instead of \arg to document parameters in order to be consistent with the rest of the codebase. llvm-svn: 163902
OpenPOWER on IntegriCloud