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* Specify fixed bit in the LDRBT encoding, which allows us to distinguish it ↵Owen Anderson2011-08-121-1/+3
| | | | | | from certain USAT16 encodings. llvm-svn: 137494
* Fix decoding of pre-indexed stores.Owen Anderson2011-08-122-0/+43
| | | | llvm-svn: 137487
* When constant double 0.0 is lowered, make sure 0 is copied directly from an Akira Hatanaka2011-08-121-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | integer register to a floating point register. It is not valid to interpret the value of a floating pointer register as part of a double precision floating point value after a single precision floating point computational or move instruction stores its result to the register. - In the test case, the following code is generated before this patch is applied: mtc1 $zero, $f2 ; unformatted copy to $f2 mov.s $f0, $f2 ; $f0 is in single format sdc1 $f12, 0($sp) mov.s $f1, $f2 ; $f1 is in single format c.eq.d $f12, $f0 ; $f0 cannot be interpreted as double - The following code is generated after this patch is applied: mtc1 $zero, $f0 ; unformatted copy to $f0 mtc1 $zero, $f1 ; unformatted copy to $f1 c.eq.d $f12, $f0 ; $f0 can be interpreted as double Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and provided the test case. llvm-svn: 137484
* switch to the new struct apis.Chris Lattner2011-08-122-5/+5
| | | | llvm-svn: 137481
* Separate decoding for STREXD and LDREXD to make each work better.Owen Anderson2011-08-122-7/+24
| | | | llvm-svn: 137476
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-126-6/+9
| | | | | | when building with assertions disabled. llvm-svn: 137460
* findDeadCallerSavedReg fix: Missing NULL terminator in register arrays.Andrew Trick2011-08-121-2/+2
| | | | | | Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it. llvm-svn: 137404
* ARM vector compare to zero instruction assembly parsing support.Jim Grosbach2011-08-111-0/+15
| | | | llvm-svn: 137389
* Enclose directive .cprestore with .set macro and nomacro to silence assemblerAkira Hatanaka2011-08-111-3/+9
| | | | | | warning. llvm-svn: 137378
* Remove no-longer-true comments. These are for the assembler, also.Jim Grosbach2011-08-111-52/+24
| | | | llvm-svn: 137375
* ARM STRT assembly parsing and encoding.Jim Grosbach2011-08-112-14/+30
| | | | llvm-svn: 137372
* Make the USAT16 operand decoder auto-generate-able.Owen Anderson2011-08-111-2/+2
| | | | llvm-svn: 137371
* Add another accidentally omitted predicate operand.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137370
* Add missing predicate operand on SMLA and friends.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137368
* ARM load shifted register pre-index fix shift value asm parser encoding.Jim Grosbach2011-08-111-1/+1
| | | | llvm-svn: 137367
* Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.Owen Anderson2011-08-111-2/+4
| | | | llvm-svn: 137364
* Making SEL decodings auto-generate-able.Owen Anderson2011-08-111-2/+2
| | | | llvm-svn: 137363
* Add a dag combine to xform 256-bit shuffles into simple vectorBruno Cardoso Lopes2011-08-111-1/+54
| | | | | | | inserts and extracts. This simple combine makes us generate only 1 instruction instead of 11 in the v8 case. llvm-svn: 137362
* Tidy up comment.Jim Grosbach2011-08-111-2/+1
| | | | llvm-svn: 137359
* Fix decoding support for STREXD and LDREXD.Owen Anderson2011-08-112-2/+29
| | | | llvm-svn: 137356
* ARM STRH assembly parsing and encoding.Jim Grosbach2011-08-113-18/+60
| | | | llvm-svn: 137353
* Add isIndirectBranch flag.Akira Hatanaka2011-08-111-1/+2
| | | | llvm-svn: 137351
* Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.Owen Anderson2011-08-111-0/+4
| | | | llvm-svn: 137347
* Tidy up. Remove unused template parameter.Jim Grosbach2011-08-112-11/+11
| | | | llvm-svn: 137345
* Improve operand validation for Thumb2 addressing modes.Owen Anderson2011-08-111-48/+50
| | | | llvm-svn: 137344
* ARM STRD assembly parsing and encoding.Jim Grosbach2011-08-113-62/+54
| | | | llvm-svn: 137342
* Continue to tighten decoding by performing more operand validation.Owen Anderson2011-08-113-2/+75
| | | | llvm-svn: 137340
* Tidy up.Jim Grosbach2011-08-111-1/+0
| | | | llvm-svn: 137339
* ARM STRBT assembly parsing and encoding.Jim Grosbach2011-08-112-25/+37
| | | | llvm-svn: 137337
* ARM STR(immediate) assembly parsing and encoding.Jim Grosbach2011-08-112-3/+22
| | | | llvm-svn: 137331
* Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137325
* Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict.Bruno Cardoso Lopes2011-08-111-2/+9
| | | | llvm-svn: 137324
* Tighten operand decoding of addrmode2 instruction. The offset register ↵Owen Anderson2011-08-112-2/+2
| | | | | | cannot be PC. llvm-svn: 137323
* Correct immediate range for shifter operands. Patch by James Molloy, with ↵Owen Anderson2011-08-112-4/+17
| | | | | | additional encoding fixes added by me. llvm-svn: 137322
* Improve error checking in the new ARM disassembler. Patch by James Molloy.Owen Anderson2011-08-111-116/+159
| | | | llvm-svn: 137320
* ARM push of a single register encodes as pre-indexed STR.Jim Grosbach2011-08-112-0/+23
| | | | | | | Per the ARM ARM, a 'push' of a single register encodes as an STR, not an STM. llvm-svn: 137318
* ARM pop of a single register encodes as post-indexed LDR.Jim Grosbach2011-08-112-0/+38
| | | | | | | Per the ARM ARM, a 'pop' of a single register encodes as an LDR, not an LDM. llvm-svn: 137316
* Add a comment, per Bruno's CR.Nadav Rotem2011-08-111-0/+3
| | | | llvm-svn: 137313
* [AVX] If the data which is going to be saved is already in two XMM registersNadav Rotem2011-08-111-0/+23
| | | | | | | | | | | | | | | | (for example, after integer operation), do not pack the registers into a YMM before saving. Its better to save as two XMM registers. Before: vinsertf128 $1, %xmm3, %ymm0, %ymm3 vinsertf128 $0, %xmm1, %ymm3, %ymm1 vmovaps %ymm1, 416(%rsp) After: vmovaps %xmm3, 416+16(%rsp) vmovaps %xmm1, 416(%rsp) llvm-svn: 137308
* Cleanup: Remove Int_ CVTSS2SI* formsBruno Cardoso Lopes2011-08-112-11/+23
| | | | llvm-svn: 137297
* Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causingBruno Cardoso Lopes2011-08-111-6/+6
| | | | | | infinite recursive calls in legalize. Fix PR10562 llvm-svn: 137296
* Use the splat index to generate the desired shuffle. Otherwise weBruno Cardoso Lopes2011-08-111-4/+4
| | | | | | | could only get undefs and the vector shuffle becomes an undef, generating wrong code. llvm-svn: 137295
* Fix X86TargetLowering::LowerExternalSymbol so that it actually works in ↵Eli Friedman2011-08-111-5/+16
| | | | | | | | non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2). Fixes PR9693. llvm-svn: 137292
* ARM LDRT assembly parsing and encoding.Jim Grosbach2011-08-102-23/+24
| | | | llvm-svn: 137282
* Tidy up. 80 columns.Jim Grosbach2011-08-101-16/+18
| | | | llvm-svn: 137277
* ARM LDRH(immediate) assembly parsing and encoding support.Jim Grosbach2011-08-102-5/+24
| | | | llvm-svn: 137260
* ARM LDRD(register) assembly parsing and encoding.Jim Grosbach2011-08-102-3/+79
| | | | | | Add support for literal encoding of #-0 along the way. llvm-svn: 137254
* Fix typo. Not quite sure how that slipped in there.Jim Grosbach2011-08-101-3/+3
| | | | llvm-svn: 137245
* ARM LDRD(immediate) assembly parsing and encoding support.Jim Grosbach2011-08-102-7/+104
| | | | llvm-svn: 137244
* When performing a truncating store, it is sometimes possible to rearrange theNadav Rotem2011-08-101-2/+79
| | | | | | | | data in-register prior to saving to memory. When we reorder the data in memory we prevent the need to save multiple scalars to memory, making a single regular store. llvm-svn: 137238
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