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authorJim Grosbach <grosbach@apple.com>2011-08-10 20:49:18 +0000
committerJim Grosbach <grosbach@apple.com>2011-08-10 20:49:18 +0000
commitf7164b2cfd807ba422f9b288f45441afc2605e1f (patch)
treef4fa2453941224fb06efa04df19a44ac03bc0d43 /llvm/lib/Target
parent5b96b806448383c930be1a126c732b4f19dc24d9 (diff)
downloadbcm5719-llvm-f7164b2cfd807ba422f9b288f45441afc2605e1f.tar.gz
bcm5719-llvm-f7164b2cfd807ba422f9b288f45441afc2605e1f.zip
Fix typo. Not quite sure how that slipped in there.
llvm-svn: 137245
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 8273ffc44ab..fcc8a6a7fd6 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -2740,9 +2740,9 @@ validateInstruction(MCInst &Inst,
"destination operands must be sequential");
return false;
}
- case ARM::STRgD:
- case ARM::STRgD_PRE:
- case ARM::STRgD_POST:
+ case ARM::STRD:
+ case ARM::STRD_PRE:
+ case ARM::STRD_POST:
case ARM::STREXD: {
// Rt2 must be Rt + 1.
unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
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