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* Add initial support for decoding NEON instructions in Thumb2 mode.Owen Anderson2011-08-102-4/+56
| | | | llvm-svn: 137236
* The following X86 pattern is incorrect:Bruno Cardoso Lopes2011-08-101-7/+0
| | | | | | | | | def : Pat<(X86Movss VR128:$src1, (bc_v4i32 (v2i64 (load addr:$src2)))), (MOVLPSrm VR128:$src1, addr:$src2)>; This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner. llvm-svn: 137227
* Tabs --> spaces.Owen Anderson2011-08-101-2/+2
| | | | llvm-svn: 137225
* Cleanups based on Nick Lewycky's feedback.Owen Anderson2011-08-101-19/+22
| | | | llvm-svn: 137224
* Rewrite some ARM InstrInfo functions to be most accepting of arbitrary ↵Owen Anderson2011-08-101-110/+115
| | | | | | register subclasses. Hopefully this fixes some buildbots. llvm-svn: 137223
* Add support for the R and Q constraints.Rafael Espindola2011-08-101-2/+22
| | | | llvm-svn: 137217
* Fix a bug in vpermilps mask checking. Fix PR10560Bruno Cardoso Lopes2011-08-101-3/+6
| | | | llvm-svn: 137194
* Push GPRnopc through a large number of instruction definitions to tighten ↵Owen Anderson2011-08-102-87/+110
| | | | | | operand decoding. llvm-svn: 137189
* Promote VMOVS to VMOVD when possible.Jakob Stoklund Olesen2011-08-091-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For better latency, we also send D-register copies down the NEON pipeline by translating them to vorr instructions. This patch promotes even S-register copies to D-register copies when possible so they can also go down the NEON pipeline. Example: vldr.32 s0, LCPI0_0 loop: vorr d1, d0, d0 loop2: ... vadd.f32 d1, d1, d16 The vorr instruction looked like this after regalloc: %S2<def> = COPY %S0, %D1<imp-def> Copies involving odd S-registers, and copies that don't define the full D-register are left alone. llvm-svn: 137182
* Tighten operand checking of register-shifted-register operands.Owen Anderson2011-08-092-5/+5
| | | | llvm-svn: 137180
* Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556Bruno Cardoso Lopes2011-08-092-0/+25
| | | | llvm-svn: 137179
* Tighten operand checking on memory barrier instructions.Owen Anderson2011-08-092-2/+25
| | | | llvm-svn: 137176
* Tighten operand checking on CPS instructions.Owen Anderson2011-08-092-0/+7
| | | | llvm-svn: 137172
* Create a new register class for the set of all GPRs except the PC. Use it ↵Owen Anderson2011-08-093-3/+21
| | | | | | to tighten our decoding of BFI. llvm-svn: 137168
* Add v16i16 and v32i8 store patternsBruno Cardoso Lopes2011-08-091-0/+8
| | | | llvm-svn: 137166
* Use fp unpack instructions to unpack int types. Until we have AVX2, thisBruno Cardoso Lopes2011-08-092-8/+34
| | | | | | is the best we can do for these patterns. This fix PR10554. llvm-svn: 137161
* Fix a couple ridiculous copy-paste errors. rdar://9914773 .Eli Friedman2011-08-091-2/+2
| | | | llvm-svn: 137160
* ARM Disassembler: sign extend branch immediates.Benjamin Kramer2011-08-091-2/+2
| | | | | | Not sure about BLXi, but this is what the old disassembler did. llvm-svn: 137156
* Silence an false-positive warning.Owen Anderson2011-08-091-1/+1
| | | | llvm-svn: 137154
* Don't generate the old-style disassembler in CMake builds either.Owen Anderson2011-08-091-1/+0
| | | | llvm-svn: 137153
* The new ARM disassembler disassembles "bx lr" as a special BX_ret ↵Benjamin Kramer2011-08-091-10/+0
| | | | | | instruction so target specific analysis isn't needed anymore. llvm-svn: 137151
* Don't continue generating the old-style decoder file.Owen Anderson2011-08-091-3/+2
| | | | llvm-svn: 137150
* ARM fix typo in pre-indexed store lowering.Jim Grosbach2011-08-091-1/+1
| | | | | | rdar://9915869 llvm-svn: 137148
* Attempt to fix CMake build.Owen Anderson2011-08-091-0/+1
| | | | llvm-svn: 137147
* Tighten Thumb1 branch predicate decoding.Owen Anderson2011-08-091-0/+3
| | | | llvm-svn: 137146
* Replace the existing ARM disassembler with a new one based on the ↵Owen Anderson2011-08-0912-7229/+2417
| | | | | | | | | | FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
* Revert r137134. It breaks some code as Eli pointed out.Bill Wendling2011-08-091-1/+1
| | | | llvm-svn: 137135
* Print out the variable declaration only if it is a declaration. Otherwise, aBill Wendling2011-08-091-1/+1
| | | | | | | 'static' variable will be emitted twice. PR10081 llvm-svn: 137134
* Reapply a more appropriate solution than in r137114. AVX supportsBruno Cardoso Lopes2011-08-091-0/+10
| | | | | | | v4f64 = sitofp v4i32. This fix PR10559. Also add support for v4i32 = fptosi v4f64. llvm-svn: 137128
* Revert r137114Bruno Cardoso Lopes2011-08-091-21/+1
| | | | llvm-svn: 137127
* PTX: Add initial support for device function callsJustin Holewinski2011-08-096-3/+144
| | | | | | - Calls are supported on SM 2.0+ for function with no return values llvm-svn: 137125
* Emitting ARM build attributes and values as ULEB, rather than char.Renato Golin2011-08-091-11/+67
| | | | llvm-svn: 137115
* Handle sitofp between v4f64 <- v4i32. Fix PR10559Bruno Cardoso Lopes2011-08-091-1/+21
| | | | llvm-svn: 137114
* Add support for avx vector fextendBruno Cardoso Lopes2011-08-091-1/+6
| | | | llvm-svn: 137105
* Add AVX versions of 128-bit sitofp and fptosiBruno Cardoso Lopes2011-08-091-0/+4
| | | | llvm-svn: 137104
* Add two patterns to match special vmovss and vmovsd cases. Also fixBruno Cardoso Lopes2011-08-091-10/+45
| | | | | | | the patterns already there to be more strict regarding the predicate. This fixes PR10558 llvm-svn: 137100
* Add missing attributes to the C++ backend's output.Bill Wendling2011-08-091-0/+3
| | | | llvm-svn: 137091
* Make LowerVSETCC aware of AVX types and add patterns to match them.Bruno Cardoso Lopes2011-08-092-3/+35
| | | | llvm-svn: 137090
* ARM parsing and encoding for LDRBT instruction.Jim Grosbach2011-08-081-11/+28
| | | | | | | Fix the instruction representation to correctly only allow post-indexed form. Add tests. llvm-svn: 137074
* Thumb1 BL instructions encoding 22 bits of displacement, not 21.Owen Anderson2011-08-081-1/+4
| | | | llvm-svn: 137073
* Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM.Jakob Stoklund Olesen2011-08-082-0/+16
| | | | | | They improve the verbose assembly. llvm-svn: 137069
* Add support for several vector shifts operations while in AVX mode. Fix PR10581Bruno Cardoso Lopes2011-08-081-10/+52
| | | | llvm-svn: 137067
* ARM load/store label parsing.Jim Grosbach2011-08-081-0/+14
| | | | | | | Allow labels for load/store instructions when parsing. There's encoding issues, still, so this doesn't work all the way through, yet. llvm-svn: 137064
* Hoist hasLoadFromStackSlot and hasStoreToStackSlot.Jakob Stoklund Olesen2011-08-082-57/+0
| | | | | | | These the methods are target-independent since they simply scan the memory operands. They can live in TargetInstrInfoImpl. llvm-svn: 137063
* Fix encodings for Thumb ASR and LSR immediate operands. They encode the ↵Owen Anderson2011-08-084-12/+35
| | | | | | range 1-32, with 32 encoded as 0. llvm-svn: 137062
* Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are ↵Eli Friedman2011-08-081-5/+6
| | | | | | correctly active without HasT2ExtractPack. PR10611. llvm-svn: 137061
* Add MCInstrAnalysis class. This allows the targets to specify own versions ↵Benjamin Kramer2011-08-081-0/+53
| | | | | | | | | of MCInstrDescs functions. - Add overrides for ARM. - Teach llvm-objdump to use this instead of plain MCInstrDesc. llvm-svn: 137059
* Don't clobber pending ST regs when FP regs are killed.Jakob Stoklund Olesen2011-08-081-0/+20
| | | | | | | | | | | | | | | | | | | X86FloatingPoint keeps track of pending ST registers for an upcoming inline asm instruction with fixed stack register constraints. It does this by remembering which FP register holds the value that should appear at a fixed stack position for the inline asm. When that FP register is killed before the inline asm, make sure to duplicate it to a scratch register, so the ST register still has a live FP reference. This could happen when the same FP register was copied to two ST registers, or when a spill instruction is inserted between the ST copy and the inline asm. This fixes PR10602. llvm-svn: 137050
* ARM load instruction shifted register index operands.Jim Grosbach2011-08-051-7/+12
| | | | | | Parsing and encoding for shifted index operands for load instructions. llvm-svn: 136986
* ARM indexed load assembly parsing and encoding.Jim Grosbach2011-08-052-13/+51
| | | | | | | More parsing support for indexed loads. Fix pre-indexed with writeback parsing for register offsets and handle basic post-indexed offsets. llvm-svn: 136982
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