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| author | Owen Anderson <resistor@mac.com> | 2011-08-09 23:25:42 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-09 23:25:42 +0000 |
| commit | e008931bf6d7dcbe4ee311b346ce1e7d81a8c9c1 (patch) | |
| tree | f83cde7c011a2a570eb40fa6cf1bc8f72ae8de4e /llvm/lib/Target | |
| parent | 4f041651ddab92f330d46bf164dc1048d5bf1c38 (diff) | |
| download | bcm5719-llvm-e008931bf6d7dcbe4ee311b346ce1e7d81a8c9c1.tar.gz bcm5719-llvm-e008931bf6d7dcbe4ee311b346ce1e7d81a8c9c1.zip | |
Tighten operand checking on memory barrier instructions.
llvm-svn: 137176
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 26 |
2 files changed, 25 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 34b3e62a2e2..e7a6b89e7b1 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -3814,6 +3814,7 @@ def MemBarrierOptOperand : AsmOperandClass { def memb_opt : Operand<i32> { let PrintMethod = "printMemBOption"; let ParserMatchClass = MemBarrierOptOperand; + let DecoderMethod = "DecodeMemBarrierOption"; } // memory barriers protect the atomic sequences diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index a3fa138ba64..4e7e582c610 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -131,6 +131,8 @@ static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, @@ -2268,8 +2270,7 @@ static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, } unsigned imm = fieldFromInstruction32(Insn, 0, 4); - Inst.addOperand(MCOperand::CreateImm(imm)); - return true; + return DecodeMemBarrierOption(Inst, imm, Address, Decoder); } unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; @@ -2347,3 +2348,24 @@ static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val, return true; } + +static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { + switch (Val) { + default: + return false; + case 0xF: // SY + case 0xE: // ST + case 0xB: // ISH + case 0xA: // ISHST + case 0x7: // NSH + case 0x6: // NSHST + case 0x3: // OSH + case 0x2: // OSHST + break; + } + + Inst.addOperand(MCOperand::CreateImm(Val)); + return true; +} + |
