| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Accept -march=i586, because gcc does (a synonym | Dale Johannesen | 2008-10-14 | 1 | -0/+1 | 
| | | | | | | | | | for pentium). Fixes gcc.target/i386/20000720-1.c gcc.target/i386/pr26826.c llvm-svn: 57528 | ||||
| * | Rename LoadX to LoadExt. | Evan Cheng | 2008-10-14 | 9 | -35/+35 | 
| | | | | | llvm-svn: 57526 | ||||
| * | Update ARM Insn encoding to get endian-ness to match the documentation (31-0 ↵ | Jim Grosbach | 2008-10-14 | 2 | -61/+57 | 
| | | | | | | | left to right) llvm-svn: 57524 | ||||
| * | Fix command-line option printing to print two spaces where needed, | Dan Gohman | 2008-10-14 | 14 | -27/+27 | 
| | | | | | | | | | | instead of requiring all "short description" strings to begin with two spaces. This makes these strings less mysterious, and it fixes some cases where short description strings mistakenly did not begin with two spaces. llvm-svn: 57521 | ||||
| * | Fix indentation. | Evan Cheng | 2008-10-14 | 1 | -2/+2 | 
| | | | | | llvm-svn: 57508 | ||||
| * | When doing the very-late shift-and address-mode optimization, | Dan Gohman | 2008-10-13 | 1 | -0/+3 | 
| | | | | | | | | | | | | | | | create a new DAG node to represent the new shift to keep the DAG consistent, even though it'll almost always be folded into the address. If a user of the resulting address has multiple uses, the nodes may get revisited by a later MatchAddress call, in which case DAG inconsistencies do matter. This fixes PR2849. llvm-svn: 57465 | ||||
| * | Update size of inst correctly with segment override. | Anton Korobeynikov | 2008-10-12 | 2 | -0/+12 | 
| | | | | | llvm-svn: 57414 | ||||
| * | Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as | Chris Lattner | 2008-10-11 | 17 | -63/+50 | 
| | | | | | | | | parameters instead of raw Constants. This prevents the constants from being selected by the isel pass, fixing PR2735. llvm-svn: 57385 | ||||
| * | Fix comment typo. | Duncan Sands | 2008-10-11 | 1 | -1/+1 | 
| | | | | | llvm-svn: 57381 | ||||
| * | Add ability to override segment (mostly for code emitter purposes). | Anton Korobeynikov | 2008-10-11 | 4 | -1/+23 | 
| | | | | | llvm-svn: 57380 | ||||
| * | Fix SSE4.1 roundss, roundsd. While the instructions have | Dale Johannesen | 2008-10-10 | 1 | -38/+52 | 
| | | | | | | | | | the same pattern as roundpd/roundps, the Intel compiler builtins do not: rounds* has an extra operand. Fixes gcc.target/i386/sse4_1-rounds[sd]-[1234].c llvm-svn: 57370 | ||||
| * | Fix a thinko and unbreak sparc default CC | Anton Korobeynikov | 2008-10-10 | 1 | -2/+2 | 
| | | | | | llvm-svn: 57368 | ||||
| * | Extend set of return registers on sparc until someone will implement MRV ↵ | Anton Korobeynikov | 2008-10-10 | 1 | -3/+3 | 
| | | | | | | | support there. At least, this will allow libgcc compile, however we are not ABI-compatible with stuff compiled with native gcc. llvm-svn: 57364 | ||||
| * | Ignore extra 'r' modifier for now | Anton Korobeynikov | 2008-10-10 | 1 | -2/+9 | 
| | | | | | llvm-svn: 57363 | ||||
| * | Use expand for smul_lohi for now | Anton Korobeynikov | 2008-10-10 | 1 | -0/+1 | 
| | | | | | llvm-svn: 57362 | ||||
| * | Add rudimentary support for 'r' register operand | Anton Korobeynikov | 2008-10-10 | 2 | -11/+70 | 
| | | | | | llvm-svn: 57359 | ||||
| * | Cleanup | Anton Korobeynikov | 2008-10-10 | 1 | -83/+82 | 
| | | | | | llvm-svn: 57358 | ||||
| * | Add rudimentary asmprinter support for printing inline asm operands for sparc. | Anton Korobeynikov | 2008-10-10 | 1 | -2/+31 | 
| | | | | | llvm-svn: 57346 | ||||
| * | Add dummy 'm' inline asm constraint handler for Sparc. I'm not sure, whether ↵ | Anton Korobeynikov | 2008-10-10 | 1 | -0/+26 | 
| | | | | | | | it is correct, however :) llvm-svn: 57345 | ||||
| * | Cleanup | Anton Korobeynikov | 2008-10-10 | 1 | -12/+12 | 
| | | | | | llvm-svn: 57344 | ||||
| * | Add a "loses information" return value to APFloat::convert | Dale Johannesen | 2008-10-09 | 3 | -4/+9 | 
| | | | | | | | | and APFloat::convertToInteger. Restore return value to IEEE754. Adjust all users accordingly. llvm-svn: 57329 | ||||
| * | Rename APFloat::convertToAPInt to bitcastToAPInt to | Dale Johannesen | 2008-10-09 | 3 | -10/+11 | 
| | | | | | | | | make it clearer what the function does. No functional change. llvm-svn: 57325 | ||||
| * | get CodeGen/Alpha/mul128.ll to work. | Chris Lattner | 2008-10-09 | 1 | -0/+2 | 
| | | | | | llvm-svn: 57318 | ||||
| * | (re)Put const weak strings in appropriate section on Darwin. | Dale Johannesen | 2008-10-08 | 1 | -1/+3 | 
| | | | | | | | g++dg/abi/key2.C llvm-svn: 57309 | ||||
| * | Comment to be explicit that the enumeration values for CondCodes matter. | Jim Grosbach | 2008-10-08 | 1 | -0/+2 | 
| | | | | | llvm-svn: 57295 | ||||
| * | Use template to distinguish between function variants. | Duncan Sands | 2008-10-08 | 1 | -5/+14 | 
| | | | | | | | | | | | | | | | GCC 4.4.0 gives an error on the "int" declaration for example saying that it has already been declared (using the "short" one). Using templates here allow the compiler to distinguish between the function to choose. Also, "llvm/Support/DataTypes.h" was not included, leading to error messages about not knowing "uint32_t" for example. Patch by Samuel Tardieu. llvm-svn: 57292 | ||||
| * | Add <cstdio> include where needed by gcc-4.4. | Duncan Sands | 2008-10-08 | 2 | -0/+2 | 
| | | | | | | | Patch by Samuel Tardieu. llvm-svn: 57291 | ||||
| * | Add MBB successors and physreg Uses in the same order that | Dan Gohman | 2008-10-07 | 1 | -7/+4 | 
| | | | | | | | | SDISel typically adds them in. This makes it a little easier to compare FastISel output with SDISel output. llvm-svn: 57266 | ||||
| * | Instead of emitting an implicit use for the super-register of | Dan Gohman | 2008-10-07 | 1 | -6/+10 | 
| | | | | | | | | | X86::CL that was used, emit an EXTRACT_SUBREG from the CL super-register to CL. This more precisely describes how the CL register is being used. llvm-svn: 57264 | ||||
| * | Unconditional branch instruction encoding fix. Needs to use ABI, not AXI, to ↵ | Jim Grosbach | 2008-10-07 | 1 | -1/+1 | 
| | | | | | | | get the proper opcode bits. llvm-svn: 57262 | ||||
| * | need ARM.h for ARMCC definition | Jim Grosbach | 2008-10-07 | 1 | -0/+1 | 
| | | | | | llvm-svn: 57261 | ||||
| * | Add an option to enable StrongPHIElimination, for ease of testing. | Owen Anderson | 2008-10-07 | 1 | -0/+7 | 
| | | | | | llvm-svn: 57259 | ||||
| * | Encode the conditional execution predicate when JITing. | Jim Grosbach | 2008-10-07 | 2 | -10/+16 | 
| | | | | | llvm-svn: 57258 | ||||
| * | Model hardwired inputs & outputs of x86 8-bit divides correctly. | Dale Johannesen | 2008-10-07 | 1 | -4/+4 | 
| | | | | | | | Fixes local RA miscompilation of gcc.c-torture/execute/20020904-1.c -O0. llvm-svn: 57257 | ||||
| * | Clarify naming and correct conditional so that CMP and CMN instructions get ↵ | Jim Grosbach | 2008-10-07 | 1 | -8/+5 | 
| | | | | | | | the Rn operand encoded properly llvm-svn: 57252 | ||||
| * | Fix Opcode values of CMP and CMN | Jim Grosbach | 2008-10-07 | 1 | -4/+4 | 
| | | | | | llvm-svn: 57251 | ||||
| * | Certain patterns involving the "movss" instruction were marked as requiring ↵ | Anders Carlsson | 2008-10-07 | 1 | -3/+3 | 
| | | | | | | | SSE2, when in reality movss is an SSE1 instruction. llvm-svn: 57246 | ||||
| * | Note that ADDC and company don't actually expand yet (missing in legalize | Andrew Lenharth | 2008-10-07 | 2 | -2/+45 | 
| | | | | | llvm-svn: 57226 | ||||
| * | Fix PR2850 and PR2863. Only generate movddup for 128-bit SSE vector shuffles. | Evan Cheng | 2008-10-06 | 1 | -0/+1 | 
| | | | | | llvm-svn: 57210 | ||||
| * | It is possible that all functions in one module are not being | Devang Patel | 2008-10-06 | 1 | -5/+2 | 
| | | | | | | | optimized for size. Set OptForSize for each function separately. llvm-svn: 57182 | ||||
| * | Remove unncessary isDeclaration() checks. | Devang Patel | 2008-10-06 | 2 | -2/+2 | 
| | | | | | llvm-svn: 57179 | ||||
| * | Emit type-correct constant null. Also fix a typo. | Anton Korobeynikov | 2008-10-05 | 1 | -7/+3 | 
| | | | | | | | Patch by Robert G. Jakabosky! llvm-svn: 57110 | ||||
| * | Fix weird think-o and unbreak build on all gcc-3.4.x-based platforms (e.g. ↵ | Anton Korobeynikov | 2008-10-05 | 3 | -98/+91 | 
| | | | | | | | mingw) llvm-svn: 57106 | ||||
| * | this case is matched now. | Chris Lattner | 2008-10-05 | 1 | -9/+1 | 
| | | | | | llvm-svn: 57096 | ||||
| * | Revert r56675 - it breaks unwinding runtime everywhere. | Anton Korobeynikov | 2008-10-04 | 1 | -18/+8 | 
| | | | | | llvm-svn: 57048 | ||||
| * | Make atomic Swap work, 64-bit on x86-32. | Dale Johannesen | 2008-10-03 | 4 | -11/+33 | 
| | | | | | | | Make it all work in non-pic mode. llvm-svn: 57034 | ||||
| * | Pass MemOperand through for 64-bit atomics on 32-bit, | Dale Johannesen | 2008-10-03 | 3 | -4/+9 | 
| | | | | | | | | incidentally making the case where the memop is a pointer deref work. Fix cmp-and-swap regression. llvm-svn: 57027 | ||||
| * | Avoid creating two TargetLowering objects for each target. | Dan Gohman | 2008-10-03 | 11 | -33/+22 | 
| | | | | | | | | | | | | | Instead, just create one, and make sure everything that needs it can access it. Previously most of the SelectionDAGISel subclasses all had their own TargetLowering object, which was redundant with the TargetLowering object in the TargetMachine subclasses, except on Sparc, where SparcTargetMachine didn't have a TargetLowering object. Change Sparc to work more like the other targets here. llvm-svn: 57016 | ||||
| * | Remove an unused field. | Dan Gohman | 2008-10-03 | 1 | -6/+1 | 
| | | | | | llvm-svn: 57014 | ||||
| * | Indexing off by one resulted in errant encoding of source register for | Jim Grosbach | 2008-10-03 | 1 | -1/+1 | 
| | | | | | | | reg->reg moves. llvm-svn: 57011 | ||||

