Fix command-line option printing to print two spaces where needed,

instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.

llvm-svn: 57521

14 files changed, 27 insertions, 27 deletions

diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 29a9d848663..a96e25f22e7 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -29,8 +29,8 @@ static cl::opt<bool> DisableIfConversion("disable-arm-if-conversion",cl::Hidden,
                               cl::desc("Disable if-conversion pass"));
 
 // Register the target.
-static RegisterTarget<ARMTargetMachine>   X("arm",   "  ARM");
-static RegisterTarget<ThumbTargetMachine> Y("thumb", "  Thumb");
+static RegisterTarget<ARMTargetMachine>   X("arm",   "ARM");
+static RegisterTarget<ThumbTargetMachine> Y("thumb", "Thumb");
 
 // No assembler printer by default
 ARMTargetMachine::AsmPrinterCtorFn ARMTargetMachine::AsmPrinterCtor = 0;
diff --git a/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp b/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
index 15c6948e494..54bfc05d126 100644
--- a/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
+++ b/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
@@ -22,7 +22,7 @@
 using namespace llvm;
 
 // Register the targets
-static RegisterTarget<AlphaTargetMachine> X("alpha", "  Alpha (incomplete)");
+static RegisterTarget<AlphaTargetMachine> X("alpha", "Alpha (incomplete)");
 
 const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const {
   return new AlphaTargetAsmInfo(*this);
diff --git a/llvm/lib/Target/CBackend/CBackend.cpp b/llvm/lib/Target/CBackend/CBackend.cpp
index 9a797480844..7ec649d0c52 100644
--- a/llvm/lib/Target/CBackend/CBackend.cpp
+++ b/llvm/lib/Target/CBackend/CBackend.cpp
@@ -49,7 +49,7 @@
 using namespace llvm;
 
 // Register the target.
-static RegisterTarget<CTargetMachine> X("c", "  C backend");
+static RegisterTarget<CTargetMachine> X("c", "C backend");
 
 namespace {
   /// CBackendNameAllUsedStructsAndMergeFunctions - This pass inserts names for
diff --git a/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp b/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp
index f0512f3b151..b8dd5aa8cfe 100644
--- a/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp
+++ b/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp
@@ -24,7 +24,7 @@ using namespace llvm;
 namespace {
   // Register the targets
   RegisterTarget<SPUTargetMachine>
-  CELLSPU("cellspu", "  STI CBEA Cell SPU");
+  CELLSPU("cellspu", "STI CBEA Cell SPU");
 }
 
 const std::pair<unsigned, int> *
diff --git a/llvm/lib/Target/CppBackend/CPPBackend.cpp b/llvm/lib/Target/CppBackend/CPPBackend.cpp
index fb836638e5f..95c4ad7dc50 100644
--- a/llvm/lib/Target/CppBackend/CPPBackend.cpp
+++ b/llvm/lib/Target/CppBackend/CPPBackend.cpp
@@ -72,7 +72,7 @@ static cl::opt<std::string> NameToGenerate("cppfor", cl::Optional,
   cl::init("!bad!"));
 
 // Register the target.
-static RegisterTarget<CPPTargetMachine> X("cpp", "  C++ backend");
+static RegisterTarget<CPPTargetMachine> X("cpp", "C++ backend");
 
 namespace {
   typedef std::vector<const Type*> TypeList;
diff --git a/llvm/lib/Target/IA64/IA64TargetMachine.cpp b/llvm/lib/Target/IA64/IA64TargetMachine.cpp
index c789a8649a2..1b811b645d7 100644
--- a/llvm/lib/Target/IA64/IA64TargetMachine.cpp
+++ b/llvm/lib/Target/IA64/IA64TargetMachine.cpp
@@ -26,7 +26,7 @@ using namespace llvm;
 extern "C" int IA64TargetMachineModule;
 int IA64TargetMachineModule = 0;
 
-static RegisterTarget<IA64TargetMachine> X("ia64", "  IA-64 (Itanium)");
+static RegisterTarget<IA64TargetMachine> X("ia64", "IA-64 (Itanium)");
 
 const TargetAsmInfo *IA64TargetMachine::createTargetAsmInfo() const {
   return new IA64TargetAsmInfo(*this);
diff --git a/llvm/lib/Target/MSIL/MSILWriter.cpp b/llvm/lib/Target/MSIL/MSILWriter.cpp
index 8e4ca1fcd97..a27c0cc688a 100644
--- a/llvm/lib/Target/MSIL/MSILWriter.cpp
+++ b/llvm/lib/Target/MSIL/MSILWriter.cpp
@@ -45,7 +45,7 @@ namespace {
 }
 
 
-static RegisterTarget<MSILTarget> X("msil", "  MSIL backend");
+static RegisterTarget<MSILTarget> X("msil", "MSIL backend");
 
 bool MSILModule::runOnModule(Module &M) {
   ModulePtr = &M;
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
index 276868cbb20..25a0eaa857c 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -20,8 +20,8 @@
 using namespace llvm;
 
 // Register the target.
-static RegisterTarget<MipsTargetMachine>    X("mips", "  Mips");
-static RegisterTarget<MipselTargetMachine>  Y("mipsel", "  Mipsel");
+static RegisterTarget<MipsTargetMachine>    X("mips", "Mips");
+static RegisterTarget<MipselTargetMachine>  Y("mipsel", "Mipsel");
 
 const TargetAsmInfo *MipsTargetMachine::
 createTargetAsmInfo() const 
diff --git a/llvm/lib/Target/PIC16/PIC16TargetMachine.cpp b/llvm/lib/Target/PIC16/PIC16TargetMachine.cpp
index 26b573a0122..df164697224 100644
--- a/llvm/lib/Target/PIC16/PIC16TargetMachine.cpp
+++ b/llvm/lib/Target/PIC16/PIC16TargetMachine.cpp
@@ -23,7 +23,7 @@ using namespace llvm;
 
 namespace {
   // Register the targets
-  RegisterTarget<PIC16TargetMachine> X("pic16", "  PIC16 14-bit");
+  RegisterTarget<PIC16TargetMachine> X("pic16", "PIC16 14-bit");
 }
 
 PIC16TargetMachine::
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 3d737515db2..22b459cb748 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -23,9 +23,9 @@ using namespace llvm;
 
 // Register the targets
 static RegisterTarget<PPC32TargetMachine>
-X("ppc32", "  PowerPC 32");
+X("ppc32", "PowerPC 32");
 static RegisterTarget<PPC64TargetMachine>
-Y("ppc64", "  PowerPC 64");
+Y("ppc64", "PowerPC 64");
 
 // No assembler printer by default
 PPCTargetMachine::AsmPrinterCtorFn PPCTargetMachine::AsmPrinterCtor = 0;
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
index cc730f82671..80af77e6808 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -19,7 +19,7 @@
 using namespace llvm;
 
 // Register the target.
-static RegisterTarget<SparcTargetMachine> X("sparc", "  SPARC");
+static RegisterTarget<SparcTargetMachine> X("sparc", "SPARC");
 
 const TargetAsmInfo *SparcTargetMachine::createTargetAsmInfo() const {
   // FIXME: Handle Solaris subtarget someday :)
diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp
index c05efd041ea..a1d6fa7eb97 100644
--- a/llvm/lib/Target/TargetMachine.cpp
+++ b/llvm/lib/Target/TargetMachine.cpp
@@ -102,13 +102,13 @@ DefRelocationModel(
   cl::init(Reloc::Default),
   cl::values(
     clEnumValN(Reloc::Default, "default",
-               "  Target default relocation model"),
+               "Target default relocation model"),
     clEnumValN(Reloc::Static, "static",
-               "  Non-relocatable code"),
+               "Non-relocatable code"),
     clEnumValN(Reloc::PIC_, "pic",
-               "  Fully relocatable, position independent code"),
+               "Fully relocatable, position independent code"),
     clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
-               "  Relocatable external references, non-relocatable code"),
+               "Relocatable external references, non-relocatable code"),
     clEnumValEnd));
 static cl::opt<llvm::CodeModel::Model, true>
 DefCodeModel(
@@ -118,15 +118,15 @@ DefCodeModel(
   cl::init(CodeModel::Default),
   cl::values(
     clEnumValN(CodeModel::Default, "default",
-               "  Target default code model"),
+               "Target default code model"),
     clEnumValN(CodeModel::Small, "small",
-               "  Small code model"),
+               "Small code model"),
     clEnumValN(CodeModel::Kernel, "kernel",
-               "  Kernel code model"),
+               "Kernel code model"),
     clEnumValN(CodeModel::Medium, "medium",
-               "  Medium code model"),
+               "Medium code model"),
     clEnumValN(CodeModel::Large, "large",
-               "  Large code model"),
+               "Large code model"),
     clEnumValEnd));
 
 static cl::opt<bool, true>
diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp
index 0d90ef61169..871e7af83f1 100644
--- a/llvm/lib/Target/X86/X86Subtarget.cpp
+++ b/llvm/lib/Target/X86/X86Subtarget.cpp
@@ -23,8 +23,8 @@ static cl::opt<X86Subtarget::AsmWriterFlavorTy>
 AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
   cl::desc("Choose style of code to emit from X86 backend:"),
   cl::values(
-    clEnumValN(X86Subtarget::ATT,   "att",   "  Emit AT&T-style assembly"),
-    clEnumValN(X86Subtarget::Intel, "intel", "  Emit Intel-style assembly"),
+    clEnumValN(X86Subtarget::ATT,   "att",   "Emit AT&T-style assembly"),
+    clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"),
     clEnumValEnd));
 
 
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index 860868adf16..923823b98cd 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -32,9 +32,9 @@ int X86TargetMachineModule = 0;
 
 // Register the target.
 static RegisterTarget<X86_32TargetMachine>
-X("x86",    "  32-bit X86: Pentium-Pro and above");
+X("x86",    "32-bit X86: Pentium-Pro and above");
 static RegisterTarget<X86_64TargetMachine>
-Y("x86-64", "  64-bit X86: EM64T and AMD64");
+Y("x86-64", "64-bit X86: EM64T and AMD64");
 
 // No assembler printer by default
 X86TargetMachine::AsmPrinterCtorFn X86TargetMachine::AsmPrinterCtor = 0;