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* Improve some const-correctness to remove a -Wcast-qual warning. No functional...Aaron Ballman2014-08-013-4/+5
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRB/LDRSB...Tilmann Scheller2014-08-011-1/+7
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRH/LDRSH...Tilmann Scheller2014-08-011-1/+5
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDR instru...Tilmann Scheller2014-08-011-0/+13
* [mips][PR19612] Fix va_arg for big-endian mode.Daniel Sanders2014-08-012-2/+68
* [PowerPC] Generate unaligned vector loads using intrinsics instead of regular...Hal Finkel2014-08-011-50/+28
* R600/SI: Fix build warningTom Stellard2014-08-011-1/+1
* [FastISel][AArch64] Fix the immediate versions of the {s|u}{add|sub}.with.ove...Juergen Ributzka2014-08-011-48/+49
* [PowerPC] Recognize consecutive memory accesses from intrinsicsHal Finkel2014-08-011-9/+63
* MS inline asm: Fix null SMLoc when 'ptr' is missing after dword & coReid Kleckner2014-08-011-1/+1
* R600/SI: Do abs/neg folding with ComplexPatternsTom Stellard2014-08-0111-658/+1034
* R600/SI: Simplify and fix handling of VOP2 in SIInstrInfo::legalizeOperandsTom Stellard2014-08-012-28/+53
* R600/SI: Fold immediates when shrinking instructionsTom Stellard2014-08-013-12/+79
* R600/SI: Fix incorrect commute operation in shrink instructions passTom Stellard2014-08-013-3/+16
* Add support for the X86 secure guard extensions instructions in assembler (SGX).Kevin Enderby2014-07-319-68/+110
* X86 MC: Don't crash on empty memory operand parensReid Kleckner2014-07-311-2/+4
* X86 MC: Reject invalid segment registers before a memory operand colonReid Kleckner2014-07-311-0/+3
* Make sure no loads resulting from load->switch DAGCombine are marked invariantLouis Gerbarg2014-07-3112-23/+28
* Fixing an -Woverloaded-virtual warnings by exposing the hidden virtual functi...Aaron Ballman2014-07-311-0/+1
* Fixing a -Wcast-qual warning in GCC. No functional changes.Aaron Ballman2014-07-311-2/+2
* [asan] Support x86 REP MOVS asm instrumentation.Evgeniy Stepanov2014-07-313-20/+153
* [FastISel][AArch64] Add basic bitcast support for conversion between float an...Juergen Ributzka2014-07-311-0/+37
* [FastISel][AArch64] Add sqrt intrinsic support.Juergen Ributzka2014-07-311-0/+19
* [FastISel][AArch64] Add MachO large code model support for function calls.Juergen Ributzka2014-07-311-10/+105
* Fix bit initializer which was one bit too long, but worked so long as we sile...Pete Cooper2014-07-311-1/+1
* Fix bit initializer which was one bit too long, but worked so long as we sile...Pete Cooper2014-07-311-1/+1
* [FastISel][AArch64 and X86] Don't emit stores for UNDEF arguments during func...Juergen Ributzka2014-07-312-0/+9
* X86 asm parser: Avoid duplicating the list of aliased instructionsReid Kleckner2014-07-311-16/+11
* Add mtpid/mfpid for BookE.Joerg Sonnenberger2014-07-301-0/+3
* Refactor TLBIVAX and add tlbsx.Joerg Sonnenberger2014-07-302-8/+10
* X86 asm parser: Use a loop to disambiguate suffixes instead of copy pasteReid Kleckner2014-07-301-38/+20
* [FastISel][AArch64] Add select folding support for the XALU intrinsics.Juergen Ributzka2014-07-301-34/+36
* [FastISel][AArch64] Add branch folding support for the XALU intrinsics.Juergen Ributzka2014-07-301-3/+77
* [FastISel][AArch64] Add {s|u}{add|sub|mul}.with.overflow intrinsic support.Juergen Ributzka2014-07-301-0/+171
* [FastISel] Move the helper function isCommutativeIntrinsic into FastISel base...Juergen Ributzka2014-07-301-12/+0
* [FastISel][AArch64] Create helper functions to create the various multiplies ...Juergen Ributzka2014-07-301-24/+70
* [FastISel][AArch64] Add support for shift-immediate.Juergen Ributzka2014-07-301-1/+101
* Add rfdi and rfmci from the e500/e500mc ISA.Joerg Sonnenberger2014-07-301-0/+3
* Add BookE's tlbre, tlbwe and tlbivax instructions.Joerg Sonnenberger2014-07-301-0/+15
* Add BookE's wrtee and wrteei instructions.Joerg Sonnenberger2014-07-301-0/+13
* SPRG 0 to 3 are valid outside BookE, so move them to the normal testJoerg Sonnenberger2014-07-302-0/+20
* R600/SI: Remove redundant setting of bits on instructions.Matt Arsenault2014-07-301-13/+2
* R600/SI: Consider adjacent offsets in getLdStBaseRegImmOfsMatt Arsenault2014-07-301-13/+39
* Add rfci instruction.Joerg Sonnenberger2014-07-291-1/+4
* mbar without argument is equivalent to mbar 0.Joerg Sonnenberger2014-07-291-0/+2
* Recognize BookE's mbar instruction.Joerg Sonnenberger2014-07-292-0/+12
* Fix typo in alias: DSIR -> DSISRJoerg Sonnenberger2014-07-291-2/+2
* Support move to/from segment register.Joerg Sonnenberger2014-07-295-0/+52
* R600/SI: Implement getLdStBaseRegImmOfsMatt Arsenault2014-07-292-0/+62
* R600/SI: Enable named operand table for DS instructionsMatt Arsenault2014-07-291-0/+1
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