summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/X86/X86Subtarget.h
Commit message (Expand)AuthorAgeFilesLines
* [x86] add and use fast horizontal vector math subtarget featureSanjay Patel2018-10-121-0/+4
* Recommit r343993: [X86] condition branches folding for three-way conditional ...Rong Xu2018-10-091-0/+4
* [X86] Revert r343993 condition branches folding for three-way conditional codesRong Xu2018-10-081-4/+0
* [X86] condition branches folding for three-way conditional codesRong Xu2018-10-081-0/+4
* [X86] Disable BMI BEXTR in X86DAGToDAGISel::matchBEXTRFromAnd unless we're on...Craig Topper2018-09-301-0/+4
* [X86] Add FeatureCMOV explicitly to all CPUs that support it. Remove FeatureC...Craig Topper2018-08-261-1/+3
* [x86/retpoline] Split the LLVM concept of retpolines into separateChandler Carruth2018-08-231-3/+16
* Remove trailing spaceFangrui Song2018-07-301-1/+1
* [X86] NFC Use member initialization in X86SubtargetGabor Buella2018-06-091-105/+106
* [x86] invpcid LLVM intrinsicGabor Buella2018-05-251-0/+4
* [X86][CET] Changing -fcf-protection behavior to comply with gcc (LLVM part)Alexander Ivchenko2018-05-181-5/+0
* [X86] ptwrite intrinsicGabor Buella2018-05-101-0/+4
* [x86] Introduce the enclv instructionGabor Buella2018-05-081-0/+1
* [x86] Introduce the pconfig instructionGabor Buella2018-05-081-0/+4
* [X86] movdiri and movdir64b instructionsGabor Buella2018-05-011-0/+8
* [X86] Revert r330638 - accidental commitGabor Buella2018-04-231-8/+0
* [X86] movdiri and movdir64b instructionsGabor Buella2018-04-231-0/+8
* [X86] WaitPKG instructionsGabor Buella2018-04-201-0/+4
* [X86] Introduce archs: goldmont-plus & tremontGabor Buella2018-04-161-1/+7
* [X86] Remove remaining itinerary support from instructions and target (PR37093)Simon Pilgrim2018-04-131-9/+0
* [X86] Introduce cldemote instructionGabor Buella2018-04-131-0/+4
* [X86] Describe wbnoinvd instructionGabor Buella2018-04-111-0/+4
* [X86] Split up -march=icelake to -client & -serverGabor Buella2018-04-101-1/+2
* [X86] Update cost model for Goldmont. Add fsqrt costs for SilvermontCraig Topper2018-03-251-0/+1
* [X86] Replace usages of X86Subtarget::hasFp256 with hasAVX. Remove hasFP256.Craig Topper2018-03-051-1/+0
* [X86] Don't make 512-bit vectors legal when preferred vector width is 256 bit...Craig Topper2018-02-111-1/+16
* [X86] Emit 11-byte or 15-byte NOPs on recent AMD targets, else default to 10-...Simon Pilgrim2018-01-291-0/+8
* Introduce the "retpoline" x86 mitigation technique for variant #2 of the spec...Chandler Carruth2018-01-221-0/+14
* Break false dependencies for POPCNT, LZCNT, TZCNTMarina Yatsina2018-01-221-0/+8
* [X86] Teach X86 codegen to use vector width preference to avoid promoting to ...Craig Topper2018-01-201-0/+11
* [X86] Add support for passing 'prefer-vector-width' function attribute into X...Craig Topper2018-01-201-1/+14
* [X86] Add intrinsic support for the RDPID instructionCraig Topper2018-01-181-0/+4
* [X86] Move HasNOPL to a subtarget feature bit. Plumb MCSubtargetInfo through ...Craig Topper2018-01-101-0/+5
* [X86] Add prefetchwt1 instruction and overhaul priorities and isel enabling f...Craig Topper2017-12-221-2/+9
* [X86][SSE] Add cpu feature for aggressive combining to variable shufflesSimon Pilgrim2017-12-191-0/+7
* X86/AArch64/ARM: Factor out common sincos_stret logic; NFCIMatthias Braun2017-12-181-4/+0
* AArch64/X86: Factor out common bzero logic; NFCMatthias Braun2017-12-181-7/+0
* Control-Flow Enforcement Technology - Shadow Stack support (LLVM side)Oren Ben Simhon2017-11-261-0/+10
* [x86][icelake]GFNICoby Tayree2017-11-261-0/+4
* [X86] Add separate intrinsics for scalar FMA4 instructions.Craig Topper2017-11-251-1/+1
* [X86] Don't report gather is legal on Skylake CPUs when AVX2/AVX512 is disabl...Craig Topper2017-11-251-0/+5
* [x86][icelake]BITALGCoby Tayree2017-11-211-0/+4
* [x86][icelake]VNNICoby Tayree2017-11-211-0/+4
* [x86][icelake]vbmi2Coby Tayree2017-11-211-0/+4
* [x86][icelake]vpclmulqdq introductionCoby Tayree2017-11-211-0/+2
* [x86][icelake]VAES introductionCoby Tayree2017-11-211-0/+2
* [LV][X86] Support of AVX2 Gathers code generation and update the LV with thisMohammed Agabaria2017-11-201-10/+11
* [X86] Add skeleton support for icelake CPU.Craig Topper2017-11-191-1/+2
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* [X86] Make FeatureAVX512 imply FeatureFMA.Craig Topper2017-11-061-1/+1
OpenPOWER on IntegriCloud