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authorGabor Buella <gabor.buella@intel.com>2018-04-23 20:00:59 +0000
committerGabor Buella <gabor.buella@intel.com>2018-04-23 20:00:59 +0000
commit213a7cda1fc775b26f94013982f252c08e57d15e (patch)
tree87ff0a7bf2820e0cb57b39dc449dea3d29dd663f /llvm/lib/Target/X86/X86Subtarget.h
parentb387b6e6dc3a7b1b1a9b5551109d124ce2afda76 (diff)
downloadbcm5719-llvm-213a7cda1fc775b26f94013982f252c08e57d15e.tar.gz
bcm5719-llvm-213a7cda1fc775b26f94013982f252c08e57d15e.zip
[X86] movdiri and movdir64b instructions
Reviewers: craig.topper llvm-svn: 330638
Diffstat (limited to 'llvm/lib/Target/X86/X86Subtarget.h')
-rw-r--r--llvm/lib/Target/X86/X86Subtarget.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h
index 59b0f0578f7..996eb01d503 100644
--- a/llvm/lib/Target/X86/X86Subtarget.h
+++ b/llvm/lib/Target/X86/X86Subtarget.h
@@ -209,6 +209,12 @@ protected:
/// Processor has Cache Line Demote instruction
bool HasCLDEMOTE;
+ /// Processor has MOVDIRI instruction (direct store integer).
+ bool HasMOVDIRI;
+
+ /// Processor has MOVDIR64B instruction (direct store 64 bytes).
+ bool HasMOVDIR64B;
+
/// Processor has Prefetch with intent to Write instruction
bool HasPREFETCHWT1;
@@ -582,6 +588,8 @@ public:
bool hasMWAITX() const { return HasMWAITX; }
bool hasCLZERO() const { return HasCLZERO; }
bool hasCLDEMOTE() const { return HasCLDEMOTE; }
+ bool hasMOVDIRI() const { return HasMOVDIRI; }
+ bool hasMOVDIR64B() const { return HasMOVDIR64B; }
bool isSHLDSlow() const { return IsSHLDSlow; }
bool isPMULLDSlow() const { return IsPMULLDSlow; }
bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
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