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* Move merge code into new helper function.Anton Korobeynikov2007-10-061-43/+34
| | | | llvm-svn: 42699
* Added storeRegToAddr, loadRegFromAddr, and unfoldMemoryOperand's.Evan Cheng2007-10-051-113/+310
| | | | llvm-svn: 42624
* Refactor code to add load / store folded instructions -> register onlyEvan Cheng2007-10-011-607/+581
| | | | | | instructions reverse map. llvm-svn: 42509
* Enabling new condition code modeling scheme.Evan Cheng2007-09-291-90/+0
| | | | llvm-svn: 42459
* TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targetsDan Gohman2007-09-271-2/+2
| | | | | | | | other than PPC64. Instead of fixing it, just remove it and fix all the places that use it to use TargetData::getPointerSize() instead, as there aren't very many. Most of the references were in DwarfWriter.cpp. llvm-svn: 42419
* Use GR64 in 64-bit mode.Evan Cheng2007-09-271-1/+4
| | | | llvm-svn: 42417
* - Added MRegisterInfo::getCrossCopyRegClass() hook. For register classes ↵Evan Cheng2007-09-261-0/+30
| | | | | | | | where reg to reg copies are not possible, this returns another register class which registers in the specified register class can be copied to (and copy back from). - X86 copyRegToReg() now supports copying between EFLAGS and GR32 / GR64 registers. llvm-svn: 42372
* Allow copyRegToReg to emit cross register classes copies.Evan Cheng2007-09-261-14/+20
| | | | | | Tested with "make check"! llvm-svn: 42346
* Correctly restore stack pointer after realignment in main() on Cygwin/Mingw32Anton Korobeynikov2007-09-261-1/+8
| | | | llvm-svn: 42332
* Missing load / store folding entries.Evan Cheng2007-09-251-0/+8
| | | | llvm-svn: 42323
* Added support for new condition code modeling scheme (i.e. physical register ↵Evan Cheng2007-09-251-0/+82
| | | | | | | | dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
* The code that used the StartLabelId label was removed, so remove theDan Gohman2007-09-241-7/+1
| | | | | | code that creates the label too. llvm-svn: 42265
* Fix several more entries in the x86 reload/remat folding tables.Dan Gohman2007-09-201-18/+18
| | | | llvm-svn: 42162
* PSHUFDmi, etc. are actually folding a load, not a store.Evan Cheng2007-09-191-3/+3
| | | | llvm-svn: 42147
* Move the entries for 64-bit CMP, IMUL, and a few others into the correctDan Gohman2007-09-181-6/+11
| | | | | | | tables so that they are eligible for reload/remat folding. And add entries for JMP and CALL. llvm-svn: 42094
* Remove RSTRegClass case from loadRegFromStackSlotDale Johannesen2007-09-171-4/+2
| | | | | | | | | and storeRegToStackSlot. Evan and I concluded this should never be needed and it appears to be true. (It if is needed, adjustment would be needed for long double to work.) llvm-svn: 42049
* Remove the assumption that FP's are either float orDale Johannesen2007-09-141-0/+8
| | | | | | | | | | | | | double from some of the many places in the optimizers it appears, and do something reasonable with x86 long double. Make APInt::dump() public, remove newline, use it to dump ConstantSDNode's. Allow APFloats in FoldingSet. Expand X86 backend handling of long doubles (conversions to/from int, mostly). llvm-svn: 41967
* Remove isReg, isImm, and isMBB, and change all their users to use Dan Gohman2007-09-141-6/+6
| | | | | | | isRegister, isImmediate, and isMachineBasicBlock, which are equivalent, and more popular. llvm-svn: 41958
* It's not safe to rematerialize MOV32r0 etc. by simply cloning the originalEvan Cheng2007-09-101-3/+22
| | | | | | | instruction. These are implemented with xor which will modify the conditional code. They should be rematerialized as move instructions. llvm-svn: 41802
* Add lengthof and endof templates that hide a lot of sizeof computations.Owen Anderson2007-09-071-8/+5
| | | | | | Patch by Sterling Stein! llvm-svn: 41758
* Added support to fold X86 load / store instructions. This allow ↵Evan Cheng2007-08-301-49/+86
| | | | | | rematerialized loads to be folded into their uses. llvm-svn: 41599
* Move getX86RegNum into X86RegisterInfo and use itDuncan Sands2007-08-291-0/+53
| | | | | | | | in the trampoline lowering. Lookup the jump and mov opcodes for the trampoline rather than hard coding them. llvm-svn: 41577
* Make sure epilogue esp adjustment is placed before any terminator and pop ↵Evan Cheng2007-07-261-2/+3
| | | | | | instructions. llvm-svn: 40538
* Heal EH handling stuff by emitting correct offsets to callee-saved registers.Anton Korobeynikov2007-07-241-1/+13
| | | | | | Pretty hackish, but code itself is dirty mess, so we won't make anything worse. :) llvm-svn: 40472
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-2/+2
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* Only adjust esp around calls in presence of alloca.Evan Cheng2007-07-191-5/+10
| | | | llvm-svn: 40028
* Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if ↵Evan Cheng2007-07-181-13/+19
| | | | | | previous instruction updates esp, fold it in. llvm-svn: 40018
* Fold prologue esp update when possible.Evan Cheng2007-07-171-1/+22
| | | | llvm-svn: 39984
* Make sure not to break eh_return.Evan Cheng2007-07-171-9/+10
| | | | llvm-svn: 39978
* Missed the case where alloca is used but the stack size (not including ↵Evan Cheng2007-07-171-17/+17
| | | | | | callee-saved portion) is zero. Thanks Dan. llvm-svn: 39974
* Use push / pop for prologues and epilogues.Evan Cheng2007-07-171-89/+135
| | | | llvm-svn: 39967
* Long live the exception handling!Anton Korobeynikov2007-07-141-6/+52
| | | | | | | | | | | | | | | This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. llvm-svn: 39855
* Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp,Dan Gohman2007-07-101-0/+20
| | | | | | | | | in addition to the intrinsic forms. Add spill-folding entries for these new instructions, and for the scalar min and max instrinsic instructions which were missing. And add some preliminary ISelLowering code for using the new non-intrinsic vector sqrt instruction, and fneg and fabs. llvm-svn: 38478
* Refactor X87 instructions. As a side effect, allDale Johannesen2007-07-041-6/+6
| | | | | | their names are changed. llvm-svn: 37876
* Fix for PR 1505 (and 1489). Rewrite X87 registerDale Johannesen2007-07-031-4/+10
| | | | | | | model to include f32 variants. Some factoring improvments forthcoming. llvm-svn: 37847
* More DWARF-related things cleanup:Anton Korobeynikov2007-05-121-7/+10
| | | | | | | | | | 1. Fix PR1380 2. Apply Duncan's patch from PR1410 3. Insert workaround for "one personality function per module" as noted in PR1414 4. Emit correct debug frames for x86/linux. This partly fixes DebugInfo/2006-11-06-StackTrace.cpp: stack trace is shown correctly, but arguments for function on top of stack are displayed incorrectly. llvm-svn: 37015
* Emit correct register move information in eh frames for X86. This allows ↵Anton Korobeynikov2007-05-021-8/+43
| | | | | | | | Shootout-C++/except to pass on x86/linux with non-llvm-compiled (e.g. "native") unwind runtime. llvm-svn: 36647
* Emit correct DWARF reg # for RA (return address) registerAnton Korobeynikov2007-05-021-1/+4
| | | | llvm-svn: 36646
* eliminateFrameIndex() change.Evan Cheng2007-05-011-1/+3
| | | | llvm-svn: 36626
* Fix for PR1348. If stack inc / dec amount is > 32-bits, issue a series of ↵Evan Cheng2007-04-261-18/+27
| | | | | | add / sub instructions. llvm-svn: 36456
* do the multiplication as signed, so that 2*-2 == -4 instead of 4294967292Chris Lattner2007-04-251-1/+2
| | | | | | when promoted to 64-bits llvm-svn: 36442
* support for >4G stack framesChris Lattner2007-04-251-3/+4
| | | | llvm-svn: 36425
* support >4G stack framesChris Lattner2007-04-251-9/+9
| | | | llvm-svn: 36423
* Add the PADDQ to the list.Bill Wendling2007-04-241-0/+1
| | | | llvm-svn: 36406
* rename X86FunctionInfo to X86MachineFunctionInfo to match the header fileChris Lattner2007-04-171-1/+1
| | | | | | it is defined in. llvm-svn: 36196
* Implemented correct stack probing on mingw/cygwin for dynamic alloca's.Anton Korobeynikov2007-04-171-4/+29
| | | | | | | Also, fixed static case in presence of eax livin. This fixes PR331 PS: Why don't we still have push/pop instructions? :) llvm-svn: 36195
* Changed to new MMX_ recipes.Bill Wendling2007-04-031-3/+3
| | | | llvm-svn: 35617
* Added MRegisterInfo hook to re-materialize an instruction.Evan Cheng2007-03-201-0/+10
| | | | llvm-svn: 35205
* Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so thatBill Wendling2007-03-081-0/+6
| | | | | | moves, loads, etc. are recognized. llvm-svn: 35031
* PEI now passes a RegScavenger ptr to eliminateFrameIndex.Evan Cheng2007-02-281-1/+2
| | | | llvm-svn: 34707
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