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* [X86] Mark LDS/LES as not being allowed in 64-bit mode.Craig Topper2016-01-261-4/+8
| | | | | | Their opcodes are used as part of the VEX prefix in 64-bit mode. Clearly the disassembler implicitly decoded them as AVX instructions in 64-bit mode, but I think the AsmParser would have encoded them. llvm-svn: 258793
* [X86] Use PS instead of TB for instructions that have PD/XS/XD variations. ↵Craig Topper2016-01-061-2/+2
| | | | | | Use OpSize32 on an instruction that has an OpSize16 variant. llvm-svn: 256918
* [X86][PKU] Add {RD,WR}PKRU intrinsicsAsaf Badouh2015-12-311-2/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D15808 llvm-svn: 256670
* [X86][PKU] Add {RD,WR}PKRU encodingAsaf Badouh2015-12-241-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D15711 llvm-svn: 256366
* Implemented Support of IA interrupt and exception handlers:Amjad Aboud2015-12-211-6/+0
| | | | | | | | http://lists.llvm.org/pipermail/cfe-dev/2015-September/045171.html Differential Revision: http://reviews.llvm.org/D15567 llvm-svn: 256155
* [X86] Add XSAVE intrinsic familyAmjad Aboud2015-10-121-22/+43
| | | | | | | | | | | | Add intrinsics for the XSAVE instructions (XSAVE/XSAVE64/XRSTOR/XRSTOR64) XSAVEOPT instructions (XSAVEOPT/XSAVEOPT64) XSAVEC instructions (XSAVEC/XSAVEC64) XSAVES instructions (XSAVES/XSAVES64/XRSTORS/XRSTORS64) Differential Revision: http://reviews.llvm.org/D13012 llvm-svn: 250029
* [X86] Change the immediate for IN/OUT instructions to u8imm so the assembly ↵Craig Topper2015-10-121-6/+6
| | | | | | parser will check the size. llvm-svn: 250012
* [X86] Remove special validation for INT immediate operand from AsmParser. ↵Craig Topper2015-10-111-1/+1
| | | | | | | | Instead mark its operand type as u8imm which will cause it to fail to match. This is more consistent with other instruction behavior. This also fixes a bug where negative immediates below -128 were not being reported as errors. llvm-svn: 249989
* [X86] Add register use/def for wrmsr and rdmsr.Craig Topper2015-02-071-0/+2
| | | | llvm-svn: 228515
* [X86] Add GETSEC instruction.Craig Topper2015-02-071-0/+6
| | | | llvm-svn: 228514
* [X86] Add xrstors/xsavec/xsaves/clflushopt/clwb/pcommit instructionsCraig Topper2015-02-051-2/+15
| | | | llvm-svn: 228283
* [X86] Remove two feature flags that covered sets of instructions that have ↵Craig Topper2015-02-051-1/+1
| | | | | | no patterns or intrinsics. Since we don't check feature flags in the assembler parser for any instruction sets, these flags don't provide any value. This frees up 2 of the fully utilized feature flags. llvm-svn: 228282
* [X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T ↵Craig Topper2015-02-031-3/+3
| | | | | | syntax. Also make them the default output. llvm-svn: 227963
* Use a different encoding for debugtrap on PS4.Alex Rosenberg2015-01-261-3/+4
| | | | llvm-svn: 227116
* [X86] Clean up whitespace as well as minor coding styleMichael Liao2014-12-041-14/+14
| | | | llvm-svn: 223339
* X86: cpuid and xgetbv write to 32-bit registers, not 64-bitReid Kleckner2014-09-041-7/+3
| | | | | | | | This fixes an issue where MS inline assembly containing xgetbv wouldn't be marked as clobbering EAX:EDX. Test for that forthcoming on the Clang side. llvm-svn: 217173
* [x86] SMAP: added HasSMAP attribute for CLAC/STAC, corrected attributesRobert Khasanov2014-08-211-1/+1
| | | | llvm-svn: 216163
* [X86] Add support for builtin to read performance monitoring counters.Andrea Di Biagio2014-06-301-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for a new builtin instruction called __builtin_ia32_rdpmc. Builtin '__builtin_ia32_rdpmc' is defined as a 'GCC builtin'; on X86, it can be used to read performance monitoring counters. It takes as input the index of the performance counter to read, and returns the value of the specified performance counter as a 64-bit number. Calls to this new builtin will map to instruction RDPMC. The index in input to the builtin call is moved to register %ECX. The result of the builtin call is the value of the specified performance counter (RDPMC would return that quantity in registers RDX:RAX). This patch: - Adds builtin int_x86_rdpmc as a GCCBuiltin; - Adds a new x86 DAG node called 'RDPMC_DAG'; - Teaches how to lower this new builtin; - Adds an ISel pattern to select instruction RDPMC; - Fixes the definition of instruction RDPMC adding %RAX and %RDX as implicit definitions, and adding %ECX as implicit use; - Adds a LLVM test to verify that the new builtin is correctly selected. llvm-svn: 212049
* [X86] Add support for Read Time Stamp Counter x86 builtin intrinsics.Andrea Di Biagio2014-04-241-1/+1
| | | | | | | | | | | | | | This patch: - Adds two new X86 builtin intrinsics ('int_x86_rdtsc' and 'int_x86_rdtscp') as GCCBuiltin intrinsics; - Teaches the backend how to lower the two new builtins; - Introduces a common function to lower READCYCLECOUNTER dag nodes and the two new rdtsc/rdtscp intrinsics; - Improves (and extends) the existing x86 test 'rdtsc.ll'; now test 'rdtsc.ll' correctly verifies that both READCYCLECOUNTER and the two new intrinsics work fine for both 64bit and 32bit Subtargets. llvm-svn: 207127
* [X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODSCraig Topper2014-02-271-6/+0
| | | | llvm-svn: 202348
* [x86] Add same itinerary to SYSEXIT64 as SYSEXIT for consistency.Craig Topper2014-02-261-2/+2
| | | | llvm-svn: 202240
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper2014-02-191-9/+9
| | | | | | 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. llvm-svn: 201641
* Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their ↵Craig Topper2014-02-181-6/+10
| | | | | | 32-bit mode counterparts for cases where there is also a OpSize16 instruction. llvm-svn: 201550
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-021-77/+81
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
* Simplify some x86 format classes and remove some ambiguities in their ↵Craig Topper2014-02-011-8/+8
| | | | | | application. llvm-svn: 200608
* x86: add implicit defs for cpuidReid Kleckner2014-01-281-2/+7
| | | | | | | This avoids miscompiling MS inline asm in LLVM where we have to infer clobbers. Test case forthcoming in Clang. llvm-svn: 200279
* [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)David Woodhouse2014-01-221-3/+6
| | | | llvm-svn: 199809
* Switch a few instructions to use RI instead I so they don't require REX_W to ↵Craig Topper2014-01-171-6/+6
| | | | | | be explicitly specified. llvm-svn: 199479
* Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ↵Craig Topper2014-01-141-2/+2
| | | | | | | | and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke. llvm-svn: 199193
* [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliasesDavid Woodhouse2014-01-081-8/+16
| | | | llvm-svn: 198755
* [x86] Add OpSize16 to instructions that need itDavid Woodhouse2014-01-081-47/+58
| | | | | | | | | This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
* Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. ↵Craig Topper2014-01-041-10/+18
| | | | | | Remove disassembler hack. llvm-svn: 198515
* Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack ↵Craig Topper2014-01-021-4/+4
| | | | | | from the disassembler table builder. llvm-svn: 198327
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-201-23/+23
| | | | | | | | | | | That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
* Changed register names (and pointer keywords) to be lower case when using ↵Craig Topper2013-07-311-38/+38
| | | | | | | | Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-111-0/+7
| | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. llvm-svn: 179266
* fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test casesKay Tiong Khoo2013-04-101-3/+3
| | | | llvm-svn: 179223
* fixed to disassemble with tab after mnemonic rather than spaceKay Tiong Khoo2013-04-101-2/+2
| | | | llvm-svn: 179215
* Add a catch-all WriteSystem SchedWrite type.Jakob Stoklund Olesen2013-03-201-1/+23
| | | | | | This is used for all the expensive system instructions. llvm-svn: 177598
* *fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo2013-02-111-4/+4
| | | | | | *added file for test cases for i386 intel syntax llvm-svn: 174900
* Rename @llvm.debugger to @llvm.debugtrap.Dan Gohman2012-05-141-1/+1
| | | | llvm-svn: 156774
* Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman2012-05-111-0/+3
| | | | | | but it generates int3 on x86 instead of ud2. llvm-svn: 156593
* Adds Intel Atom scheduling latencies to X86InstrSystem.td.Preston Gurd2012-05-041-138/+152
| | | | llvm-svn: 156194
* Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax.Bill Wendling2012-03-101-5/+5
| | | | | | Patch by Kay Tiong Khoo! llvm-svn: 152487
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-3/+3
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Fix asm string wrt variants.Devang Patel2012-01-091-6/+6
| | | | llvm-svn: 147805
* Add intrinsics and feature flag for read/write FS/GS base instructions. Also ↵Craig Topper2011-10-301-13/+21
| | | | | | add AVX2 feature flag. llvm-svn: 143319
* Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix andKevin Enderby2011-10-271-3/+2
| | | | | | | not depend on In32BitMode. Use the sysexitq mnemonic for the version with the REX.W prefix and only allow it only In64BitMode. rdar://9738584 llvm-svn: 143112
* Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, ↵Craig Topper2011-10-161-0/+9
| | | | | | VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. llvm-svn: 142117
* Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.Craig Topper2011-10-071-0/+23
| | | | llvm-svn: 141358
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