bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Expand)	Author	Age	Files	Lines
*	[X86] Create a new instruction format to handle 4VOp3 encoding. This saves on...	Craig Topper	2016-08-22	1	-10/+10
*	[X86] Use u8imm for the immediate type for all shift and rotate instructions....	Craig Topper	2015-10-12	1	-70/+70
*	Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"	Sergey Dmitrouk	2015-04-28	1	-2/+2
*	Revert "[DebugInfo] Add debug locations to constant SD nodes"	Daniel Jasper	2015-04-28	1	-2/+2
*	[DebugInfo] Add debug locations to constant SD nodes	Sergey Dmitrouk	2015-04-28	1	-2/+2
*	[X86] Don't mark the shift by 1 instructions as isConvertibleToThreeAddress. ...	Craig Topper	2015-01-07	1	-1/+1
*	[X86] Clean up whitespace as well as minor coding style	Michael Liao	2014-12-04	1	-26/+26
*	Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.	Craig Topper	2014-11-26	1	-2/+2
*	Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ...	Craig Topper	2014-02-02	1	-112/+100
*	Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ...	Craig Topper	2014-01-14	1	-2/+2
*	[x86] Add OpSize16 to instructions that need it	David Woodhouse	2014-01-08	1	-50/+53
*	Changed register names (and pointer keywords) to be lower case when using Int...	Craig Topper	2013-07-31	1	-68/+68
*	Fix typo. Change %cl to CL in Intel pattern.	Craig Topper	2013-07-22	1	-1/+1
*	whitespace	Nadav Rotem	2013-05-04	1	-2/+2
*	Annotate shifts and rotates with SchedRW lists.	Jakob Stoklund Olesen	2013-03-25	1	-17/+37
*	Add hasSideEffects=0 to some shift and rotate instructions. None of which are...	Craig Topper	2012-12-27	1	-1/+5
*	Add SARX/SHRX/SHLX code generation support	Michael Liao	2012-09-26	1	-0/+55
*	Add RORX code generation support	Michael Liao	2012-09-26	1	-0/+23
*	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...	Jia Liu	2012-02-18	1	-3/+3
*	Instruction scheduling itinerary for Intel Atom.	Andrew Trick	2012-02-01	1	-192/+287
*	Intel style asm variant does not need '%' prefix.	Devang Patel	2012-01-03	1	-14/+14
*	Add X86 SARX, SHRX, and SHLX instructions.	Craig Topper	2011-10-23	1	-18/+32
*	Add X86 RORX instruction	Craig Topper	2011-10-23	1	-0/+21
*	rework the rotate-by-1 instructions to be defined like the	Chris Lattner	2010-11-06	1	-16/+16
*	integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight.	Chris Lattner	2010-10-05	1	-81/+249
*	move 32-bit shift and rotates out to their own file.	Chris Lattner	2010-10-05	1	-0/+578