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path: root/llvm/lib/Target/X86/X86InstrArithmetic.td
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* Fix the operand encoding in the test instruction.Rafael Espindola2015-03-311-4/+4
* [X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LE...Craig Topper2015-01-081-2/+2
* [X86] Make isel select the 2-byte register form of INC/DEC even in non-64-bit...Craig Topper2015-01-061-72/+42
* [X86] Remove the predicates from the register forms of the 2-byte inc and dec...Craig Topper2015-01-051-43/+22
* [X86] Fix some cases where some 8-bit instructions were marked as being conve...Craig Topper2014-12-291-18/+24
* [X86] Add the 0x82 instructions to the disassebmler. They are identical in fu...Craig Topper2014-12-291-6/+35
* [x86] Refactor some tablegen instruction info classes slightly to prepare for...Craig Topper2014-12-291-29/+28
* [x86] Remove unused classes from tablegen instruction info.Craig Topper2014-12-291-23/+0
* [X86] Remove unnecessary 'In64BitMode' predicate for instructions that alread...Craig Topper2014-12-181-14/+11
* [X86] Clean up whitespace as well as minor coding styleMichael Liao2014-12-041-1/+1
* Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.Craig Topper2014-11-261-8/+8
* [x86] Broadwell: ADOX/ADCX. Added _addcarryx_u{32|64} intrinsics to LLVM.Robert Khasanov2014-08-211-20/+28
* [X86] Mark pseudo instruction TEST8ri_NOEREX as hasSIdeEffects=0.Akira Hatanaka2014-07-101-2/+4
* Add an x86 prefix encoding for instructions that would decode to a different ...Craig Topper2014-02-181-2/+2
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ...Craig Topper2014-02-021-75/+69
* [x86] Fix signed relocations for i64i32imm operandsDavid Woodhouse2014-01-301-9/+9
* Switch a few instructions to use RI instead I so they don't require REX_W to ...Craig Topper2014-01-171-8/+8
* Add OpSize16 to the two byte forms of INC/DEC that we only use in 64-bit mode...Craig Topper2014-01-151-5/+5
* Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ...Craig Topper2014-01-141-4/+4
* [x86] Add OpSize16 to instructions that need itDavid Woodhouse2014-01-081-31/+40
* Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode ...Craig Topper2014-01-051-2/+3
* Add a new x86 specific instruction flag to force some isCodeGenOnly instructi...Craig Topper2014-01-051-0/+2
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-201-13/+13
* Add disassembler support for long encodings for INC/DEC in 32-bit mode.Craig Topper2013-10-071-1/+15
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-131-28/+40
* Changed register names (and pointer keywords) to be lower case when using Int...Craig Topper2013-07-311-16/+16
* Fix IMULX machine model. Multiple def operands require multiple SchedWrites.Andrew Trick2013-06-211-4/+4
* Correct the def registers for the 8bit x86 divide instructions toEric Christopher2013-06-111-4/+4
* X86: Fix Defs/Uses for insts that imp-def/imp-use both an A-register and EFLAGS.Ahmed Bougacha2013-05-291-66/+74
* Annotate the remaining x86 instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-261-2/+2
* Annotate remaining IIC_BIN_* instructions.Jakob Stoklund Olesen2013-03-201-5/+10
* Annotate X86 arithmetic instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-181-60/+112
* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-141-0/+46
* Two changes relevant to LEA and x32:David Sehr2013-02-011-2/+2
* Remove # from the beginning and end of def names.Craig Topper2013-01-071-123/+123
* Recommit r171461 which was incorrectly reverted. Mark DIV/IDIV instructions h...Craig Topper2013-01-051-1/+1
* Revert "Mark DIV/IDIV instructions hasSideEffects=1 because they can trap whe...Michael Gottesman2013-01-031-1/+1
* Mark DIV/IDIV instructions hasSideEffects=1 because they can trap when dividi...Craig Topper2013-01-031-1/+1
* Mark the divide instructions as hasSideEffects=0.Craig Topper2012-12-271-0/+2
* Add hasSideEffects=0 to CMP*rr_REV.Craig Topper2012-12-271-0/+1
* Mark the AL/AX/EAX forms of the basic arithmetic operations has never having ...Craig Topper2012-12-261-43/+44
* Mark all the _REV instructions as not having side effects. They aren't really...Craig Topper2012-12-261-0/+1
* Simplify BMI ANDN matching to use patterns instead of a DAG combine. Also add...Craig Topper2012-12-171-2/+13
* X86: enable CSE between CMP and SUBManman Ren2012-08-081-0/+2
* X86: remove redundant cmp against zero.Manman Ren2012-07-181-1/+1
* X86: peephole optimization to remove cmp instructionManman Ren2012-07-061-0/+2
* Revert r157831Manman Ren2012-06-031-2/+0
* X86: peephole optimization to remove cmp instructionManman Ren2012-06-011-0/+2
* This patch adds X86 instruction itineraries, which were missed by thePreston Gurd2012-04-091-28/+30
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-3/+3
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