| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [X86] Don't use RCP14 and RSQRT14 for reciprocal estimations or for legacy SS... | Craig Topper | 2017-11-04 | 1 | -1/+3 |
| * | [X86] Make sure we don't create locked inc/dec instructions when the carry fl... | Craig Topper | 2017-10-30 | 1 | -1/+1 |
| * | Revert r307036 because of PR34919. | Wei Mi | 2017-10-12 | 1 | -13/+0 |
| * | [X86] Provide the LSDA pointer with RIP relative addressing if necessary | Martin Storsjo | 2017-10-03 | 1 | -0/+1 |
| * | [X86][XOP] Merge rotation opcodes with AVX512 equivalents. NFCI. | Simon Pilgrim | 2017-09-26 | 1 | -2/+0 |
| * | [X86] Make IFMA instructions during isel so we can fold broadcast loads. | Craig Topper | 2017-09-24 | 1 | -0/+4 |
| * | [X86] Move the getInsertVINSERTImmediate and getExtractVEXTRACTImmediate help... | Craig Topper | 2017-09-23 | 1 | -20/+0 |
| * | [X86] Remove is the isVINSERT*Index/isVEXTRACT*Index predicates from isel. | Craig Topper | 2017-09-23 | 1 | -20/+0 |
| * | [X86] Remove the X86ISD::MOVLHPD. Lowering doesn't use it and it's not a real... | Craig Topper | 2017-09-18 | 1 | -1/+0 |
| * | [x86] enable storeOfVectorConstantIsCheap() target hook | Sanjay Patel | 2017-09-16 | 1 | -0/+7 |
| * | [X86] Move matching of (and (srl/sra, C), (1<<C) - 1) to BEXTR/BEXTRI instruc... | Craig Topper | 2017-09-12 | 1 | -3/+0 |
| * | [X86] Remove portions of r275950 that are no longer needed with i1 not being ... | Craig Topper | 2017-09-11 | 1 | -2/+0 |
| * | [X86] Limit store merge size when implicitfloat is enabled (PR34421) | Simon Pilgrim | 2017-09-05 | 1 | -0/+3 |
| * | [DAG] convert vector select-of-constants to logic/math | Sanjay Patel | 2017-08-24 | 1 | -3/+1 |
| * | [X86] Remove X86ISD::FMADD in favor ISD::FMA | Craig Topper | 2017-08-23 | 1 | -1/+1 |
| * | [X86] Refactoring of X86TargetLowering::EmitLoweredSelect. NFC. | Amjad Aboud | 2017-08-17 | 1 | -0/+4 |
| * | [X86][ARM][TargetLowering] Add SrcVT to isExtractSubvectorCheap | Craig Topper | 2017-08-13 | 1 | -1/+2 |
| * | [X86][DAG] Switch X86 Target to post-legalized store merge | Nirav Dave | 2017-08-11 | 1 | -0/+4 |
| * | DAGCombiner: Extend reduceBuildVecToTrunc to handle non-zero offset | Zvi Rackover | 2017-07-26 | 1 | -0/+13 |
| * | TargetLowering: Change isShuffleMaskLegal's mask argument type to ArrayRef<in... | Zvi Rackover | 2017-07-26 | 1 | -2/+1 |
| * | [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess... | Michael Zuckerman | 2017-07-26 | 1 | -0/+42 |
| * | [SystemZ, LoopStrengthReduce] | Jonas Paulsson | 2017-07-21 | 1 | -1/+2 |
| * | DAGCombine: Combine BUILD_VECTOR to TRUNCATE | Zvi Rackover | 2017-07-03 | 1 | -0/+13 |
| * | Supported lowerInterleavedStore() in X86InterleavedAccess. | Farhana Aleen | 2017-06-22 | 1 | -0/+6 |
| * | [X86] Add support for "probe-stack" attribute | whitequark | 2017-06-22 | 1 | -0/+2 |
| * | AVX-512: Lowering Masked Gather intrinsic - fixed a bug | Elena Demikhovsky | 2017-06-22 | 1 | -1/+17 |
| * | Remove ADDC, ADDE, SUBC, SUBE and SETCCE support from the X86 backend, use th... | Amaury Sechet | 2017-06-01 | 1 | -1/+0 |
| * | Do not legalize large setcc with setcce, introduce setcccarry and do it with ... | Amaury Sechet | 2017-06-01 | 1 | -0/+1 |
| * | [X86][LWP] Add llvm support for LWP instructions (reapplied). | Simon Pilgrim | 2017-05-03 | 1 | -0/+3 |
| * | Revert rL302028 due to accidental line ending changes. | Simon Pilgrim | 2017-05-03 | 1 | -3/+0 |
| * | [X86][LWP] Add llvm support for LWP instructions. | Simon Pilgrim | 2017-05-03 | 1 | -0/+3 |
| * | TargetLowering: Add finalizeLowering() function; NFC | Matthias Braun | 2017-04-28 | 1 | -4/+3 |
| * | [SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and simplifyDem... | Craig Topper | 2017-04-28 | 1 | -2/+1 |
| * | DAG: Make mayBeEmittedAsTailCall parameter const | Matt Arsenault | 2017-04-18 | 1 | -1/+1 |
| * | [DAGCombiner] add and use TLI hook to convert and-of-seteq / or-of-setne to b... | Sanjay Patel | 2017-04-05 | 1 | -0/+4 |
| * | [DAGCombiner] Add vector demanded elements support to ComputeNumSignBits | Simon Pilgrim | 2017-03-31 | 1 | -0/+1 |
| * | [DAGCombiner] Add vector demanded elements support to computeKnownBitsForTarg... | Simon Pilgrim | 2017-03-31 | 1 | -0/+1 |
| * | [X86] Removed old comment. NFCI. | Simon Pilgrim | 2017-03-29 | 1 | -2/+1 |
| * | [x86] use PMOVMSK to replace memcmp libcalls for 16-byte equality | Sanjay Patel | 2017-03-25 | 1 | -0/+3 |
| * | Remove the subtarget argument from LowerFP_TO_INT since there's one | Eric Christopher | 2017-03-23 | 1 | -2/+1 |
| * | Rename AttributeSet to AttributeList | Reid Kleckner | 2017-03-21 | 1 | -1/+1 |
| * | Make library calls sensitive to regparm module flag (Fixes PR3997). | Nirav Dave | 2017-03-18 | 1 | -0/+3 |
| * | [SelectionDAG] Add a signed integer absolute ISD node | Simon Pilgrim | 2017-03-14 | 1 | -3/+0 |
| * | Disable Callee Saved Registers | Oren Ben Simhon | 2017-03-14 | 1 | -1/+2 |
| * | [DAGCombiner] allow transforming (select Cond, C +/- 1, C) to (add(ext Cond), C) | Sanjay Patel | 2017-03-04 | 1 | -0/+4 |
| * | [AVX-512] Separate the fadd/fsub/fmul/fdiv/fmax/fmin with rounding mode ISD o... | Craig Topper | 2017-02-24 | 1 | -6/+6 |
| * | [AVX-512] Allow legacy scalar min/max intrinsics to select EVEX instructions ... | Craig Topper | 2017-02-22 | 1 | -0/+3 |
| * | [CodeGenPrepare] Sink and duplicate more 'and' instructions. | Geoff Berry | 2017-02-21 | 1 | -0/+2 |
| * | [X86] Fix EXTRACT_VECTOR_ELT with variable index from v32i16 and v64i8 vector. | Igor Breger | 2017-02-20 | 1 | -2/+1 |
| * | [X86][MMX] Remove the (long time) unused MMX_PINSRW ISD opcode. | Simon Pilgrim | 2017-02-09 | 1 | -1/+1 |
