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path: root/llvm/lib/Target/X86/X86ISelLowering.cpp
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* Revert [X86] EltsFromConsecutiveLoads - support common source loadsReid Kleckner2019-07-181-63/+5
* [X86] EltsFromConsecutiveLoads - support common source loadsSimon Pilgrim2019-07-181-5/+63
* [X86] Disable combineConcatVectors for vXi1 vectors.Craig Topper2019-07-181-0/+4
* [X86] Make sure we mark 128/256 MLOAD as Legal with VLX when min-legal-vector...Craig Topper2019-07-171-5/+7
* [x86] use more phadd for reductionsSanjay Patel2019-07-161-0/+54
* [X86] In combineStore, don't convert v2f32 load/store pairs to f64 loads/stores.Craig Topper2019-07-161-3/+2
* Fix parameter name comments using clang-tidy. NFC.Rui Ueyama2019-07-161-2/+2
* [x86] try to keep FP casted+truncated+extracted vector element out of GPRsSanjay Patel2019-07-151-0/+39
* [X86] Return UNDEF from LowerScalarImmediateShift when the shift amount is ou...Craig Topper2019-07-151-2/+5
* [X86] isTargetShuffleEquivalent - assert the expected mask is correctly forme...Simon Pilgrim2019-07-151-0/+2
* [X86] Separate the memory size of vzext_load/vextract_store from the element ...Craig Topper2019-07-151-26/+47
* [x86] simplify cmov with same true/false operandsSanjay Patel2019-07-131-0/+4
* [X86] Merge negated ISD::SUB nodes into X86ISD::SUB equivalent (PR40483)Sanjay Patel2019-07-111-7/+7
* [X86] Remove unused variable. NFCCraig Topper2019-07-101-1/+0
* [X86] EltsFromConsecutiveLoads - clean up element size calcs. NFCI.Simon Pilgrim2019-07-101-14/+12
* [X86] EltsFromConsecutiveLoads - remove duplicate check for element size. NFCI.Simon Pilgrim2019-07-101-6/+0
* [X86] EltsFromConsecutiveLoads - ensure element reg/store sizes are the same ...Simon Pilgrim2019-07-101-3/+5
* [X86] EltsFromConsecutiveLoads - cleanup Zero/Undef/Load element collection. ...Simon Pilgrim2019-07-101-12/+17
* [X86] EltsFromConsecutiveLoads - LDBase is non-null. NFCI.Simon Pilgrim2019-07-101-6/+4
* [X86] EltsFromConsecutiveLoads - store Loads on a per-element basis. NFCI.Simon Pilgrim2019-07-101-9/+9
* [X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable supportSimon Pilgrim2019-07-101-7/+15
* [X86] Limit getTargetConstantFromNode to only work on NormalLoads not extendi...Craig Topper2019-07-101-1/+1
* [X86] Don't form extloads in combineExtInVec unless the load extension is legal.Craig Topper2019-07-091-7/+9
* [X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCast...Craig Topper2019-07-091-3/+9
* [X86] LowerToHorizontalOp - use count_if to count non-UNDEF ops. NFCI.Simon Pilgrim2019-07-091-5/+2
* Standardize on MSVC behavior for triples with no environmentReid Kleckner2019-07-081-6/+4
* [X86] ISD::INSERT_SUBVECTOR - use uint64_t index. NFCI.Simon Pilgrim2019-07-081-4/+4
* [X86] SimplifyDemandedVectorEltsForTargetNode - fix shadow variable warning. ...Simon Pilgrim2019-07-061-3/+3
* [X86] LowerBuildVectorv16i8 - pull out repeated getOperand() call. NFCI.Simon Pilgrim2019-07-061-3/+3
* [X86][SSE] LowerINSERT_VECTOR_ELT - early out for out of range indicesSimon Pilgrim2019-07-051-3/+3
* [X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(conc...Simon Pilgrim2019-07-041-8/+8
* [X86] Use pointer sized indices instead of i32 for EXTRACT_VECTOR_ELT and INS...Craig Topper2019-07-041-2/+2
* [X86] ComputeNumSignBitsForTargetNode - add target shuffle support.Simon Pilgrim2019-07-031-1/+50
* [X86][AVX] combineX86ShufflesRecursively - peek through extract_subvectorSimon Pilgrim2019-07-031-20/+25
* [X86][AVX] Combine vpermi(bitcast(x)) -> bitcast(vpermi(x))Simon Pilgrim2019-07-031-0/+16
* [X86][AVX] combineX86ShuffleChainWithExtract - add number of non-zero extract...Simon Pilgrim2019-07-031-0/+3
* [X86][SSE] lowerUINT_TO_FP_v2i32 - explicitly cast half word to doubleSimon Pilgrim2019-07-031-1/+1
* [X86][SSE] LowerINSERT_VECTOR_ELT - ensure insertion index correctness. NFCI.Simon Pilgrim2019-07-031-1/+2
* [X86][SSE] LowerScalarImmediateShift - ensure shift amount correctness. NFCI.Simon Pilgrim2019-07-031-2/+4
* Fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-07-031-1/+1
* [X86] LowerFunnelShift - use modulo constant shift amount.Simon Pilgrim2019-07-031-1/+1
* [X86] Add a DAG combine for turning *_extend_vector_inreg+load into an approp...Craig Topper2019-07-021-5/+27
* [X86] getTargetConstantBitsFromNode - remove unnecessary getZExtValue() (PR42...Simon Pilgrim2019-07-021-2/+1
* [X86][AVX] combineX86ShuffleChain - pull out CombineShuffleWithExtract lambda...Simon Pilgrim2019-07-021-105/+116
* [X86] resolveTargetShuffleInputsAndMask - add repeated input handling.Simon Pilgrim2019-07-021-7/+22
* [X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patternsCraig Topper2019-07-011-0/+39
* [X86] Add widenSubVector to size in bits helper. NFCI.Simon Pilgrim2019-07-011-4/+16
* [X86] CombineShuffleWithExtract - updated description comments. NFCI.Simon Pilgrim2019-07-011-4/+4
* [X86] Add a DAG combine to replace vector loads feeding a v4i32->v2f64 CVTSI2...Craig Topper2019-07-011-0/+28
* [X86] Custom lower AVX masked loads to masked load and vselect instead of sel...Craig Topper2019-06-301-11/+29
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