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path: root/llvm/lib/Target/X86/X86ISelLowering.cpp
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* [X86] Fix DecodeVPERMVMask to handle cases where the constant pool entry has ...Craig Topper2016-10-181-1/+1
* [AVX-512] Fix DecodeVPERMV3Mask to handle cases where the constant pool entry...Craig Topper2016-10-181-2/+4
* [AVX-512] Add shuffle combining support for vpermi2var shuffles derived from ...Craig Topper2016-10-171-0/+14
* [AVX-512] Add support for turning a 256-bit load that goes to both halfs of a...Craig Topper2016-10-161-13/+22
* [MachineMemOperand] Move synchronization scope and atomic orderings from SDNo...Konstantin Zhuravlyov2016-10-151-5/+2
* [safestack] Use non-thread-local unsafe stack pointer for Contiki OSDavid L Kreitzer2016-10-141-0/+3
* [X86] Take advantage of the lzcnt instruction on btver2 architectures when OR...Pierre Gousseau2016-10-141-0/+114
* CodeGen: use MSVC division on windows itaniumSaleem Abdulrasool2016-10-131-1/+2
* CodeGen: adjust floating point operations in Windows itaniumSaleem Abdulrasool2016-10-131-1/+2
* [X86][AVX512] Fix sext v32i1 -> v32i8 lowering.Igor Breger2016-10-131-1/+1
* Silence unused warning in non-assert builds.Daniel Jasper2016-10-131-3/+3
* [AVX-512] Teach shuffle lowering to recognize 512-bit zero extends.Craig Topper2016-10-131-2/+27
* [X86] Simplify the lowering code for extracting and inserting subvectors.Craig Topper2016-10-131-24/+21
* Create llvm.addressofreturnaddress intrinsicAlbert Gutowski2016-10-121-0/+7
* [x86][inline-asm][llvm] accept 'v' constraintMichael Zuckerman2016-10-101-0/+15
* DAG: Setting Masked-Expand-Load as a variant of Masked-Load nodeElena Demikhovsky2016-10-091-11/+12
* [Target] move reciprocal estimate settings from TargetOptions to TargetLoweringSanjay Patel2016-10-041-2/+12
* [x86, SSE/AVX] allow 128/256-bit lowering for copysign vector intrinsics (PR3...Sanjay Patel2016-10-031-17/+27
* [X86][AVX2] Add support for combining target shuffles to VPERMD/VPERMPSSimon Pilgrim2016-10-021-3/+23
* [X86][AVX] Ensure broadcast loads respect dependenciesSimon Pilgrim2016-10-021-0/+11
* [X86] Don't set i64 ADDC/ADDE/SUBC/SUBE as Custom if the target isn't 64-bit....Craig Topper2016-10-021-7/+4
* [X86] Fix indentation. NFCCraig Topper2016-10-021-1/+1
* Fix signed/unsigned warningSimon Pilgrim2016-10-011-2/+2
* [X86][SSE] Add support for combining target shuffles to binary BLENDSimon Pilgrim2016-10-011-4/+30
* [X86][SSE] Always combine target shuffles to MOVSD/MOVSSSimon Pilgrim2016-10-011-8/+4
* Revert r282835 "[AVX-512] Always use the full 32 register vector classes for ...Craig Topper2016-09-301-15/+30
* [X86] Add AVX-512 VTs to findRepresentativeClass as well as v16i16 which was ...Craig Topper2016-09-301-3/+5
* [AVX-512] Always use the full 32 register vector classes for addRegisterClass...Craig Topper2016-09-301-30/+15
* Strip trailing whitespaceSimon Pilgrim2016-09-281-1/+1
* [x86] add folds for FP logic with vector zerosSanjay Patel2016-09-271-17/+34
* [x86] use isNullFPConstant(); NFCISanjay Patel2016-09-271-40/+35
* [X86][avx512] Fix bug in masked compress store.Ayman Musa2016-09-261-5/+5
* [X86] Remove what appears to be leftover MMX code involving (v1i64 scalar_to_...Craig Topper2016-09-251-4/+0
* [AVX-512] Don't use two opcodes for INTR_TYPE_SCALAR_MASK_RM. The handling wa...Craig Topper2016-09-251-2/+1
* [X86] Teach combineShuffle to avoid creating floating point operations with i...Craig Topper2016-09-241-7/+12
* [AVX-512] Split scalar version of X86ISD::SELECT into a separate opcode becau...Craig Topper2016-09-241-2/+4
* [x86] don't try to create a vector integer inst for an SSE1 target (PR30512)Sanjay Patel2016-09-241-3/+4
* [x86] fix FCOPYSIGN lowering to create constants instead of ConstantPool loadsSanjay Patel2016-09-231-43/+22
* [AVX-512] Split X86ISD::VFPROUND and X86ISD::VFPEXT into separate opcodes for...Craig Topper2016-09-231-0/+4
* [AVX-512] Add separate ISD opcodes for each form of CVT instructions. Don't r...Craig Topper2016-09-231-4/+12
* [AVX-512] Use different ISD opcodes for some of the scalar intrinsic lowering...Craig Topper2016-09-231-0/+7
* i386 does not support optimized swifterror handlingArnold Schwaighofer2016-09-221-0/+4
* [AVX-512] Split the 3 different usages of the X86ISD::FSETCC opcode into 3 di...Craig Topper2016-09-211-6/+9
* [AVX-512] Simplify handling of INTR_TYPE_1OP_MASK_RM to remove support for th...Craig Topper2016-09-211-7/+1
* [AVX-512] Don't lower avx512 vcvtps2ph/vcvtph2ps nodes to ISD::FP16_TO_FP/ISD...Craig Topper2016-09-211-1/+3
* AVX-512: Fixed a bug in lowering saturated operations on KNL.Elena Demikhovsky2016-09-201-2/+8
* [AVX-512] Use 512-bit vcvtps2ph/vcvtph2ps to implement fp_to_f16/f16_to_fp wh...Craig Topper2016-09-201-1/+1
* [x86] fix variable names; NFCSanjay Patel2016-09-201-22/+23
* [x86] use getSignBit() to simplify code; NFCISanjay Patel2016-09-191-4/+3
* [AVX-512] Add support for lowering fp_to_f16 and f16_to_fp when VLX is suppor...Craig Topper2016-09-191-1/+2
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