| Commit message (Collapse) | Author | Age | Files | Lines |
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Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
llvm-svn: 75379
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llvm-svn: 75236
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to use isGlobalStubReference instead of GVRequiresExtraLoad
(which should really be part of isel).
llvm-svn: 75234
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llvm-svn: 75232
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template. Also convert it to take a MachineOperand instead of a GV*
llvm-svn: 75227
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Finish converting lib/Target.
llvm-svn: 75043
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cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)
llvm-svn: 75018
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cleanup, removed some #includes and moved Object Code Emitter out-of-line.
llvm-svn: 74813
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a base register. We just ignore it for now.
llvm-svn: 74374
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llvm-svn: 72697
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JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray
llvm-svn: 72631
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decoding. Essentially, they both map to the same column in the "opcode
extensions for one- and two-byte opcodes" table in the x86 manual. The RawFrm
complicates decoding this.
Instead, use opcode 0x01, prefix 0x01, and form MRM1r. Then have the code
emitter special case these, a la [SML]FENCE.
llvm-svn: 72556
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llvm-svn: 71520
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more place. This fixes a bunch of x86-64 JIT regressions.
(Introduced when the value of the magic constant changed
in 68645. At the time apparently nobody noticed; failures
were hidden in 70343-70439 by an unrelated bug, so showed
up again as "new" failures in 70440.)
llvm-svn: 71106
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needed. It causes a lot of x86_64 JIT failures.
llvm-svn: 70986
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- Synchronize instruction length computation code in X86InstrInfo with code in X86CodeEmitter.cpp
Patch by Zoltan Varga.
llvm-svn: 70929
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Tested by bootstrapping llvm-gcc and using that to build llvm.
llvm-svn: 68645
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builds.
--- Reverse-merging (from foreign repository) r68552 into '.':
U test/CodeGen/X86/tls8.ll
U test/CodeGen/X86/tls10.ll
U test/CodeGen/X86/tls2.ll
U test/CodeGen/X86/tls6.ll
U lib/Target/X86/X86Instr64bit.td
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86RegisterInfo.cpp
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86CodeEmitter.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86InstrInfo.h
U lib/Target/X86/X86ISelDAGToDAG.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86ISelLowering.h
U lib/Target/X86/X86InstrInfo.cpp
U lib/Target/X86/X86InstrBuilder.h
U lib/Target/X86/X86RegisterInfo.td
llvm-svn: 68560
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This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.
Will work on it and on X86-64 support.
llvm-svn: 68552
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llvm-svn: 67949
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of operands in an address in so many places.
llvm-svn: 67945
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assembly. 2. Fixed JIT encoding by making the address pc-relative.
llvm-svn: 66803
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some overflow issues. Patch by Thomas Jablin.
llvm-svn: 60828
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llvm-svn: 59677
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llvm-svn: 59004
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llvm-svn: 58949
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indirect gv reference. Please don't call it lazy.
llvm-svn: 58746
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llvm-svn: 58528
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llvm-svn: 58141
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fixes a bunch of test-suite JIT failures on x86-64 in
-relocation-model=static mode.
llvm-svn: 58066
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except they do not have any operands. The RegModRM byte is encoded with register number 0.
llvm-svn: 57692
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llvm-svn: 57414
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llvm-svn: 57381
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llvm-svn: 57380
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isReg, etc., from isRegister, etc.
llvm-svn: 57006
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llvm-svn: 55779
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This unbreaks explicit reg vars inside JIT, which are
implemented in such hacky way :)
llvm-svn: 55128
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llvm-svn: 55117
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llvm-svn: 54700
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non_lazy_ptr mechanism on x86-64 Darwin JIT. Fixes a bunch
of last night's failures.
llvm-svn: 54692
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model, except for external calls; this makes
addressing modes PC-relative. Incomplete.
The assertion at the top of Emitter::runOnMachineFunction
was obviously bogus (always true) so I removed it.
If someone knows what the correct test should be to cover
all the various targets, please fix.
llvm-svn: 54656
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the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
llvm-svn: 52943
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changed.
llvm-svn: 51291
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This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
llvm-svn: 51091
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- Remove unused instructions.
llvm-svn: 49921
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instruction. X86, PowerPC and ARM are implemented
llvm-svn: 49809
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example, extractps in 64bit mode: 66 REX 0F 3A 17, not 66 0F 3A REX 17.
llvm-svn: 49157
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llvm-svn: 48447
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independent one: TargetInstrInfo::IMPLICIT_DEF.
llvm-svn: 48380
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llvm-svn: 48359
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