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author | Bill Wendling <isanbard@gmail.com> | 2009-05-28 23:40:46 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2009-05-28 23:40:46 +0000 |
commit | 2e09bd3d34a24454d774e5f3ee6865de0914205a (patch) | |
tree | 02fc695847ecb19cac977e644f8bc8b0e823ac15 /llvm/lib/Target/X86/X86CodeEmitter.cpp | |
parent | d6ab8744dc68e7dec176a5899e1d68a4a8de91f0 (diff) | |
download | bcm5719-llvm-2e09bd3d34a24454d774e5f3ee6865de0914205a.tar.gz bcm5719-llvm-2e09bd3d34a24454d774e5f3ee6865de0914205a.zip |
The MONITOR and MWAIT instructions have insufficient information for
decoding. Essentially, they both map to the same column in the "opcode
extensions for one- and two-byte opcodes" table in the x86 manual. The RawFrm
complicates decoding this.
Instead, use opcode 0x01, prefix 0x01, and form MRM1r. Then have the code
emitter special case these, a la [SML]FENCE.
llvm-svn: 72556
Diffstat (limited to 'llvm/lib/Target/X86/X86CodeEmitter.cpp')
-rw-r--r-- | llvm/lib/Target/X86/X86CodeEmitter.cpp | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86CodeEmitter.cpp b/llvm/lib/Target/X86/X86CodeEmitter.cpp index 63bf18d157f..efd64e05ec5 100644 --- a/llvm/lib/Target/X86/X86CodeEmitter.cpp +++ b/llvm/lib/Target/X86/X86CodeEmitter.cpp @@ -671,13 +671,26 @@ void Emitter::emitInstruction(const MachineInstr &MI, case X86II::MRM6r: case X86II::MRM7r: { MCE.emitByte(BaseOpcode); - // Special handling of lfence and mfence. + // Special handling of lfence, mfence, monitor, and mwait. if (Desc->getOpcode() == X86::LFENCE || - Desc->getOpcode() == X86::MFENCE) + Desc->getOpcode() == X86::MFENCE || + Desc->getOpcode() == X86::MONITOR || + Desc->getOpcode() == X86::MWAIT) { emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r); - else + + switch (Desc->getOpcode()) { + default: break; + case X86::MONITOR: + MCE.emitByte(0xC8); + break; + case X86::MWAIT: + MCE.emitByte(0xC9); + break; + } + } else { emitRegModRMByte(MI.getOperand(CurOp++).getReg(), (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r); + } if (CurOp != NumOps) { const MachineOperand &MO1 = MI.getOperand(CurOp++); |