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* [X86] Remove the single AdSize indicator and replace it with separate ↵Craig Topper2014-12-241-10/+4
| | | | | | | | AdSize16/32/64 flags. This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler. llvm-svn: 224809
* x86: Emit LOCK prefix after DATA16JF Bastien2014-12-151-4/+6
| | | | | | | | | | | | | | Summary: x86 allows either ordering for the LOCK and DATA16 prefixes, but using GCC+GAS leads to different code generation than using LLVM. This change matches the order that GAS emits the x86 prefixes when a semicolon isn't used in inline assembly (see tc-i386.c comment before define LOCK_PREFIX), and helps simplify tooling that operates on the instruction's byte sequence (such as NaCl's validator). This change shouldn't have any performance impact. Test Plan: ninja check Reviewers: craig.topper, jvoung Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D6630 llvm-svn: 224283
* [X86] Clean up whitespace as well as minor coding styleMichael Liao2014-12-041-2/+2
| | | | llvm-svn: 223339
* Use uint64_t as the type for the X86 TSFlag format enum. Allows removal of ↵Craig Topper2014-11-111-31/+26
| | | | | | the VEXShift hack that was used to access the higher bits of TSFlags. llvm-svn: 221673
* Add support for the X86 secure guard extensions instructions in assembler (SGX).Kevin Enderby2014-07-311-14/+17
| | | | | | | | | | | | | This allows assembling the two new instructions, encls and enclu for the SKX processor model. Note the diffs are a bigger than what might think, but to fit the new MRM_CF and MRM_D7 in things in the right places things had to be renumbered and shuffled down causing a bit more diffs. rdar://16228228 llvm-svn: 214460
* [X86] AVX512: Use the TD version of CD8_Scale in the assemblerAdam Nemet2014-07-171-40/+7
| | | | | | | | | | | Passes the computed scaling factor in TSFlags rather than the old attributes. Also removes the C++ version of computing the scaling factor (MemObjSize) along with the asserts added by the previous patch. No functional change. llvm-svn: 213279
* [X86] AVX512: Move compressed displacement logic to TDAdam Nemet2014-07-171-0/+4
| | | | | | | | | | | | | | | This does not actually move the logic yet but reimplements it in the Tablegen language. Then asserts that the new implementation results in the same value. The next patch will remove the assert and the temporary use of the TSFlags and remove the C++ implementation. The formula requires a limited form of the logical left and right operators. I implemented these with the bit-extract/insert operator (i.e. blah{bits}). No functional change. llvm-svn: 213278
* [X86] AVX512: Improve readability of isCDisp8Adam Nemet2014-07-111-3/+12
| | | | | | | | No functional change. As I was trying to understand this function, I found that variables were reused with confusing names and the broadcast case was a bit too implicit. Hopefully, this is an improvement. llvm-svn: 212795
* [X86] AVX512: Simplify logic in isCDisp8Adam Nemet2014-07-111-6/+6
| | | | | | | | | | | | It was computing the VL/n case as: MemObjSize = VectorByteSize / ElemByteSize / Divider * ElemByteSize ElemByteSize not only falls out but VectorByteSize/Divider now actually matches the definition of VL/n. Also some formatting fixes. llvm-svn: 212794
* AVX-512: changes in intrinsicsElena Demikhovsky2014-05-121-0/+4
| | | | | | | | | 1) Changed gather and scatter intrinsics. Now they are aligned with GCC built-ins. There is no more non-masked form. Masked intrinsic receives -1 if all lanes are executed. 2) I changed the function that works with intrinsics inside X86ISelLowering.cpp. I put all intrinsics in one table. I did it for INTRINSICS_W_CHAIN and plan to put all intrinsics from WO_CHAIN set to the same table in order to avoid the long-long "switch". (I wanted to use static map initialization that allowed by C++11 but I wasn't able to compile it on VS2012). 3) I added gather/scatter prefetch intrinsics. 4) I fixed MRMm encoding for masked instructions. llvm-svn: 208522
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-2/+2
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* Handle _GLOBAL_OFFSET_TABLE_ in 64 bit mode.Rafael Espindola2014-04-211-1/+7
| | | | | | | | | With this MC is able to handle _GLOBAL_OFFSET_TABLE_ in 64 bit mode, which is needed for medium and large code models. This fixes pr19470. llvm-svn: 206793
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-091-1/+1
| | | | | | class. llvm-svn: 203418
* AVX-512: fixed comressed displacement - by Robert KhazanovElena Demikhovsky2014-03-061-1/+1
| | | | llvm-svn: 203096
* Remove special FP opcode maps and instead add enough MRM_XX formats to ↵Craig Topper2014-02-191-7/+34
| | | | | | handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. llvm-svn: 201649
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper2014-02-191-17/+11
| | | | | | 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. llvm-svn: 201641
* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-101-4/+12
| | | | | | | | | | Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. llvm-svn: 201065
* Revert r201059 and r201060.Bob Wilson2014-02-101-11/+4
| | | | | | | | r201059 appears to cause a crash in a bootstrapped build of clang. Craig isn't available to look at it right now, so I'm reverting it while he investigates. llvm-svn: 201064
* Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' ↵Craig Topper2014-02-101-4/+11
| | | | | | field of modrm byte as a don't care value. Will allow for simplification of disassembler code. llvm-svn: 201059
* AVX-512: fixed a bug in EVEX encoding (the bug appeared after r200624)Elena Demikhovsky2014-02-051-2/+4
| | | | llvm-svn: 200837
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-021-4/+5
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
* Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field ↵Craig Topper2014-02-021-33/+37
| | | | | | in TSFlags. llvm-svn: 200624
* Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the ↵Craig Topper2014-01-311-90/+33
| | | | | | TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. llvm-svn: 200522
* Move REP out of the Prefix field of the X86 format. Give it its own bit. It ↵Craig Topper2014-01-311-2/+1
| | | | | | had special handling anyway and this enables a future patch. llvm-svn: 200520
* Move address override handling in X86MCCodeEmitter to a place where it works ↵Craig Topper2014-01-311-46/+43
| | | | | | for VEX encoded instructions too. This allows 32-bit addressing to work in 64-bit mode. llvm-svn: 200516
* [x86] Fix signed relocations for i64i32imm operandsDavid Woodhouse2014-01-301-10/+7
| | | | | | | | | These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32. Kill the horrid and incomplete special case and FIXME in EncodeInstruction() and set things up so it can infer the signedness from the ImmType just like it can the size and whether it's PC-relative. llvm-svn: 200495
* Delete MCSubtargetInfo data members from target MCCodeEmitter classesDavid Woodhouse2014-01-281-38/+38
| | | | | | | | The subtarget info is explicitly passed to the EncodeInstruction method and we should use that subtarget info to influence any encoding decisions. llvm-svn: 200350
* Explictly pass MCSubtargetInfo to MCCodeEmitter::EncodeInstruction()David Woodhouse2014-01-281-2/+4
| | | | llvm-svn: 200348
* [x86] Silence unused diReg variable warning in non-asserting buildsDavid Woodhouse2014-01-221-4/+3
| | | | llvm-svn: 199812
* ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+18
| | | | llvm-svn: 199806
* [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+10
| | | | llvm-svn: 199804
* [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+13
| | | | llvm-svn: 199803
* Replace duplicated code with a existing helper function.Craig Topper2014-01-171-16/+1
| | | | llvm-svn: 199468
* Allow x86 mov instructions to/from memory with absolute address to be ↵Craig Topper2014-01-161-13/+20
| | | | | | encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
* Remove use of OpSize for populating VEX_PP field. A prefix encoding is now ↵Craig Topper2014-01-161-10/+4
| | | | | | used instead. Simplify some other code. No functional changes intended. llvm-svn: 199353
* Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ↵Craig Topper2014-01-141-0/+19
| | | | | | | | and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke. llvm-svn: 199193
* AVX-512: Embedded Rounding Control - encoding and printingElena Demikhovsky2014-01-131-9/+15
| | | | | | Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC. llvm-svn: 199102
* [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse2014-01-081-4/+9
| | | | | | | | | | It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
* [x86] Use 16-bit addressing where possible in 16-bit modeDavid Woodhouse2014-01-081-14/+18
| | | | | | | | | Where "where possible" means that it's an immediate value and it's below 0x10000. In fact GAS will either truncate or error with larger values, and will insist on using the addr32 prefix to get 32-bit addressing. So perhaps we should do that, in a later patch. llvm-svn: 198758
* [x86] Fix JCXZ,JECXZ_32 for 16-bit modeDavid Woodhouse2014-01-081-1/+5
| | | | | | | JCXZ should have the 0x67 prefix only if we're in 32-bit mode, so make that appropriately conditional. And JECXZ needs the prefix instead. llvm-svn: 198757
* Remove SegOvrBits from X86 TSFlags since they weren't being used.Craig Topper2014-01-061-23/+13
| | | | llvm-svn: 198588
* Remove argument to fix build bot failure.Craig Topper2014-01-061-1/+1
| | | | llvm-svn: 198587
* Add OpSize16 bit, for instructions which need 0x66 prefix in 16-bit modeCraig Topper2014-01-061-2/+1
| | | | | | | | | | | | | | | | | The 0x66 prefix toggles between 16-bit and 32-bit addressing mode. So in 32-bit mode it is used to switch to 16-bit addressing mode for the following instruction, while in 16-bit mode it's the other way round — it's used to switch to 32-bit mode instead. Thus, emit the 0x66 prefix byte for OpSize only in 32-bit (and 64-bit) mode, and introduce a new OpSize16 bit which is used in 16-bit mode instead. This is just the basic infrastructure for that change; a subsequent patch will add the new OpSize16 bit to the 32-bit instructions that need it. Patch from David Woodhouse. llvm-svn: 198586
* [x86] Add basic support for .code16Craig Topper2014-01-061-2/+10
| | | | | | | | | | | This is not really expected to work right yet. Mostly because we will still emit the OpSize (0x66) prefix in all the wrong places, along with a number of other corner cases. Those will all be fixed in the subsequent commits. Patch from David Woodhouse. llvm-svn: 198584
* Fix ModR/M byte output for 16-bit addressing modes (PR18220)Craig Topper2014-01-051-0/+60
| | | | | | | | | Add some tests to validate correct register selection, including a fix to an existing test which was requiring the *wrong* output. Patch from David Woodhouse. llvm-svn: 198566
* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-011-8/+29
| | | | | | | Printing rounding control. Enncoding for EVEX_RC (rounding control). llvm-svn: 198277
* Remove MRMInitReg form now that it's last use is gone.Craig Topper2013-12-311-4/+0
| | | | llvm-svn: 198257
* Merge case statements to remove redundant code.Craig Topper2013-12-301-18/+12
| | | | llvm-svn: 198241
* Change type of XOP flag in code emitters to a bool. Remove a some unneeded ↵Craig Topper2013-09-291-7/+4
| | | | | | cases from switch. llvm-svn: 191632
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