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* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-33/+33
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-131-9/+10
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-10/+9
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-241-9/+10
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-241-10/+9
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* [X86] Fix diassembler crash on AVX512 cmpps/cmppd with immediate that ↵Craig Topper2015-03-021-20/+22
| | | | | | doesn't fit in 5-bits. Fixes PR22743. llvm-svn: 230924
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-9/+10
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-10/+9
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* [X86] Add support for parsing and printing the mnemonic aliases for the XOP ↵Craig Topper2015-02-131-8/+24
| | | | | | VPCOM instructions. llvm-svn: 229078
* [X86] Teach disassembler to handle illegal immediates on AVX512 integer ↵Craig Topper2015-01-281-0/+129
| | | | | | compare instructions. llvm-svn: 227302
* [X86] Convert all the i8imm used by SSE and AVX instructions to u8imm.Craig Topper2015-01-211-14/+2
| | | | | | This makes the assembler check their size and removes a hack from the disassembler to avoid sign extending the immediate. llvm-svn: 226645
* [X86] Remove some unused TYPE enums from the disassembler.Craig Topper2015-01-071-5/+0
| | | | llvm-svn: 225343
* Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd ↵Craig Topper2014-12-261-0/+48
| | | | | | instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4. llvm-svn: 224846
* [X86] Clean up whitespace as well as minor coding styleMichael Liao2014-12-041-38/+38
| | | | llvm-svn: 223339
* Pass an ArrayRef to MCDisassembler::getInstruction.Rafael Espindola2014-11-121-8/+20
| | | | | | | | | | | | With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t> instead of a MemoryObject. Even on X86 there is a maximum size an instruction can have. Given that, it seems way simpler and more efficient to just pass an ArrayRef to the disassembler instead of a MemoryObject and have it do a virtual call every time it wants some extra bytes. llvm-svn: 221751
* Misc style fixes. NFC.Rafael Espindola2014-11-101-37/+25
| | | | | | | | | | | | | This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
* [X86] AVX512: Add disassembler support for compressed displacementAdam Nemet2014-07-171-1/+1
| | | | | | | | | | | | There are two parts here. First is to modify tablegen to adjust the encoding type ENCODING_RM with the scaling factor. The second is to use the new encoding types to compute the correct displacement in the decoder. Fixes <rdar://problem/17608489> llvm-svn: 213281
* Fix gcc -Wsign-compare warning in X86DisassemblerTables.cpp.Patrik Hagglund2014-04-281-5/+3
| | | | | | | | | | X86_MAX_OPERANDS is changed to unsigned. Also, add range-based for loops for affected loops. This in turn needed an ArrayRef instead of a pointer-to-array in InternalInstruction. llvm-svn: 207413
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-1/+1
| | | | llvm-svn: 207197
* X86Disassembler - fixed a bug in immediate printElena Demikhovsky2014-04-231-1/+1
| | | | llvm-svn: 206953
* [cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth2014-04-221-5/+5
| | | | | | | | | | | | system headers above the includes of generated '.inc' files that actually contain code. In a few targets this was already done pretty consistently, but it wasn't done *really* consistently anywhere. It is strictly cleaner IMO and necessary in a bunch of places where the DEBUG_TYPE is referenced from the generated code. Consistency with the necessary places trumps. Hopefully the build bots are OK with the movement of intrin.h... llvm-svn: 206838
* [Modules] Make Support/Debug.h modular. This requires it to not changeChandler Carruth2014-04-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | behavior based on other files defining DEBUG_TYPE, which means it cannot define DEBUG_TYPE at all. This is actually better IMO as it forces folks to define relevant DEBUG_TYPEs for their files. However, it requires all files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't already. I've updated all such files in LLVM and will do the same for other upstream projects. This still leaves one important change in how LLVM uses the DEBUG_TYPE macro going forward: we need to only define the macro *after* header files have been #include-ed. Previously, this wasn't possible because Debug.h required the macro to be pre-defined. This commit removes that. By defining DEBUG_TYPE after the includes two things are fixed: - Header files that need to provide a DEBUG_TYPE for some inline code can do so by defining the macro before their inline code and undef-ing it afterward so the macro does not escape. - We no longer have rampant ODR violations due to including headers with different DEBUG_TYPE definitions. This may be mostly an academic violation today, but with modules these types of violations are easy to check for and potentially very relevant. Where necessary to suppor headers with DEBUG_TYPE, I have moved the definitions below the includes in this commit. I plan to move the rest of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big enough. The comments in Debug.h, which were hilariously out of date already, have been updated to reflect the recommended practice going forward. llvm-svn: 206822
* What year is it! This file has no reason to be written in C, and has doubly noRichard Smith2014-04-201-5/+5
| | | | | | | | | | reason to expose a global symbol 'decodeInstruction' nor to pollute the global scope with a bunch of external linkage entities (some of which conflict with others elsewhere in LLVM). This is just the initial transition to C++; more cleanups to follow. llvm-svn: 206717
* [MC] Require an MCContext when constructing an MCDisassembler.Lang Hames2014-04-151-3/+5
| | | | | | | | | | | | | | | | This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). llvm-svn: 206241
* [X86] unique_ptr'ify one of X86GenericDisassembler's members.Lang Hames2014-04-131-10/+7
| | | | llvm-svn: 206127
* X86Disassembler.cpp: Fix @param introduced in r199804. [-Wdocumentation]NAKAMURA Takumi2014-01-231-1/+0
| | | | llvm-svn: 199855
* Remove param doxygen comment for non-existing parameter.Benjamin Kramer2014-01-221-1/+0
| | | | | | Found by -Wdocumentation. llvm-svn: 199814
* [x86] Fix uninitialized variable warning in translate{Src,Dst}IndexDavid Woodhouse2014-01-221-2/+6
| | | | llvm-svn: 199811
* [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+22
| | | | llvm-svn: 199804
* [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+25
| | | | llvm-svn: 199803
* [x86] Infer disassembler mode from SubtargetInfo feature bitsDavid Woodhouse2014-01-201-13/+23
| | | | | | | | | | | | Aside from cleaning up the code, this also adds support for the -code16 environment and actually enables the MODE_16BIT mode that was previously not accessible. There is no point adding any testing for 16-bit yet though; basically nothing will work because we aren't handling the OpSize prefix correctly for 16-bit mode. llvm-svn: 199649
* Allow x86 mov instructions to/from memory with absolute address to be ↵Craig Topper2014-01-161-11/+18
| | | | | | encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
* X86Disassembler.cpp: Prune stray @return on translateFPRegister(). ↵NAKAMURA Takumi2014-01-011-1/+0
| | | | | | [-Wdocumentation] llvm-svn: 198279
* Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are ↵Craig Topper2014-01-011-12/+4
| | | | | | really more like OrRegFrm so we don't need a difference since we can just mask bits. llvm-svn: 198278
* Second attempt at Removing special form of AddRegFrm used by FP ↵Craig Topper2014-01-011-2/+2
| | | | | | instructions. These instructions can be handled by MRMXr instead. llvm-svn: 198276
* AVX-512: decoder for AVX-512, made by Alexey Bader.Elena Demikhovsky2013-12-251-3/+34
| | | | llvm-svn: 198013
* First round of fixes for the x86 fixes for the x86 move accumulator from/to ↵Craig Topper2013-08-251-17/+12
| | | | | | | | | | | | | | memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
* Remove trailing whitespace.Craig Topper2013-08-241-1/+1
| | | | llvm-svn: 189178
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-0/+5
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Update the X86 disassembler to use xacquire and xrelease when appropriate.Kevin Enderby2013-06-201-0/+9
| | | | | | | | | | | | | | | | | This is a bit tricky as the xacquire and xrelease hints use the same bytes, 0xf2 and 0xf3, as the repne and rep prefixes. Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease and repne/xacquire. So to make this work a boolean was added the InternalInstruction struct as part of the Prefix state which is set with the added logic in readPrefixes() when decoding an instruction to determine if these prefix bytes are to be disassembled as xacquire or xrelease. Then we let the matcher pick the normal prefix instructionID and we change the Opcode after that when it is set into the MCInst being created. rdar://11019859 llvm-svn: 184490
* Add MCSymbolizer for symbolic/annotated disassembly.Ahmed Bougacha2013-05-241-97/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a basic first step towards symbolization of disassembled instructions. This used to be done using externally provided (C API) callbacks. This patch introduces: - the MCSymbolizer class, that mimics the same functions that were used in the X86 and ARM disassemblers to symbolize immediate operands and to annotate loads based off PC (for things like c string literals). - the MCExternalSymbolizer class, which implements the old C API. - the MCRelocationInfo class, which provides a way for targets to translate relocations (either object::RelocationRef, or disassembler C API VariantKinds) to MCExprs. - the MCObjectSymbolizer class, which does symbolization using what it finds in an object::ObjectFile. This makes simple symbolization (with no fancy relocation stuff) work for all object formats! - x86-64 Mach-O and ELF MCRelocationInfos. - A basic ARM Mach-O MCRelocationInfo, that provides just enough to support the C API VariantKinds. Most of what works in otool (the only user of the old symbolization API that I know of) for x86-64 symbolic disassembly (-tvV) works, namely: - symbol references: call _foo; jmp 15 <_foo+50> - relocations: call _foo-_bar; call _foo-4 - __cf?string: leaq 193(%rip), %rax ## literal pool for "hello" Stub support is the main missing part (because libObject doesn't know, among other things, about mach-o indirect symbols). As for the MCSymbolizer API, instead of relying on the disassemblers to call the tryAdding* methods, maybe this could be done automagically using InstrInfo? For instance, even though PC-relative LEAs are used to get the address of string literals in a typical Mach-O file, a MOV would be used in an ELF file. And right now, the explicit symbolization only recognizes PC-relative LEAs. InstrInfo should have already have most of what is needed to know what to symbolize, so this can definitely be improved. I'd also like to remove object::RelocationRef::getValueString (it seems only used by relocation printing in objdump), as simply printing the created MCExpr is definitely enough (and cleaner than string concats). llvm-svn: 182625
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-191-6/+0
| | | | llvm-svn: 170578
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-2/+1
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Use const properly so that we dont remove const qualifier from region and MIIRoman Divacky2012-09-051-5/+5
| | | | | | by casting. Found with gcc48. llvm-svn: 163247
* Add support for converting llvm.fma to fma4 instructions.Craig Topper2012-08-311-0/+2
| | | | llvm-svn: 162999
* Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper2012-08-011-4/+3
| | | | | | used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. llvm-svn: 161101
* Fix a bug in the x86 disassembler's symbolic disassembly support for Jcc-JumpKevin Enderby2012-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | if Condition Is Met instuctions that was not correctly determining the target instruction. So for a jne rel32 instruction: % cat x.s .byte 0x0f, 0x85, 0x09, 0x00, 0x00, 0x00 % as x.s it was incorrectly deterining the target: % otool -q -tv a.out a.out: (__TEXT,__text) section 0000000000000000 jne 0xd and with the fix it gets this correct as: % otool -q -tv a.out a.out: (__TEXT,__text) section 0000000000000000 jne 0xf rdar://11505997 llvm-svn: 160694
* Remove tabs.Bill Wendling2012-07-191-9/+9
| | | | llvm-svn: 160477
* X86: add more GATHER intrinsics in LLVMManman Ren2012-06-291-10/+18
| | | | | | | | | | | | | | | Corrected type for index of llvm.x86.avx2.gather.d.pd.256 from 256-bit to 128-bit. Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256 from 256-bit to 128-bit. Support the following intrinsics: llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256 llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256 llvm-svn: 159402
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-261-1/+26
| | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. llvm-svn: 159221
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