summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
diff options
context:
space:
mode:
authorCraig Topper <craig.topper@gmail.com>2012-08-01 07:39:18 +0000
committerCraig Topper <craig.topper@gmail.com>2012-08-01 07:39:18 +0000
commitb8aec0881901d33a7bc7d4d93255127e655cf253 (patch)
tree13ae30cd45010d3fbc53ee645014ff74681b74cb /llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
parent13a39c6f549f36391e583c53a654bfaa089e1933 (diff)
downloadbcm5719-llvm-b8aec0881901d33a7bc7d4d93255127e655cf253.tar.gz
bcm5719-llvm-b8aec0881901d33a7bc7d4d93255127e655cf253.zip
Add more indirection to the disassembler tables to reduce amount of space used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data.
llvm-svn: 161101
Diffstat (limited to 'llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp')
-rw-r--r--llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp7
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
index e936b521073..5039887e1a2 100644
--- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -762,8 +762,7 @@ static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
translateRegister(mcInst, insn.vvvv);
return false;
case ENCODING_DUP:
- return translateOperand(mcInst,
- insn.spec->operands[operand.type - TYPE_DUP0],
+ return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
insn, Dis);
}
}
@@ -789,8 +788,8 @@ static bool translateInstruction(MCInst &mcInst,
insn.numImmediatesTranslated = 0;
for (index = 0; index < X86_MAX_OPERANDS; ++index) {
- if (insn.spec->operands[index].encoding != ENCODING_NONE) {
- if (translateOperand(mcInst, insn.spec->operands[index], insn, Dis)) {
+ if (insn.operands[index].encoding != ENCODING_NONE) {
+ if (translateOperand(mcInst, insn.operands[index], insn, Dis)) {
return true;
}
}
OpenPOWER on IntegriCloud