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* [WebAssembly] SIMD negThomas Lively2018-09-141-0/+30
| | | | | | | | | | | | Summary: Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52009 llvm-svn: 342296
* [WebAssembly] Fix signature of `main` in FixFunctionBitcastsSam Clegg2018-09-131-2/+4
| | | | | | | | | Also, add a check to ensure that when main has the expected signature we do not create a wrapper. Differential Revision: https://reviews.llvm.org/D51562 llvm-svn: 342157
* Remove isAsCheapAsAMove from v128.constThomas Lively2018-09-131-1/+1
| | | | llvm-svn: 342106
* Remove isAsCheapAsAMove from mem opsThomas Lively2018-09-131-2/+2
| | | | llvm-svn: 342105
* [WebAssembly] Add missing SIMD instruction attributesThomas Lively2018-09-131-2/+3
| | | | | | | | | | | | | | Summary: These attributes are copied from equivalent instructions in WebAssemblyInstrInfo.td. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51518 llvm-svn: 342104
* [WebAssembly] Make tied inline asm operands work againHeejin Ahn2018-09-121-0/+5
| | | | | | | | | | | | | | | | | Summary: rL341389 broke code with tied register operands in inline assembly. For example, `asm("" : "=r"(var) : "0"(var));` The code above specifies the input operand to be in the same register with the output operand, tying the two register. This patch makes this kind of code work again. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, eraman, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51991 llvm-svn: 342084
* [WebAssembly] SIMD comparisonsThomas Lively2018-09-122-1/+55
| | | | | | | | | | | | | | | | Summary: Match the ordering semantics of non-vector comparisons. For floating point comparisons that do not correspond to instructions, the tests check that some vector comparison instruction was emitted but do not care about the full implementation. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51765 llvm-svn: 342064
* [Target] Untangle disassemblersBenjamin Kramer2018-09-101-1/+0
| | | | | | | Disassemblers cannot depend on main target headers. The same is true for MCTargetDesc, but there's a lot more cleanup needed for that. llvm-svn: 341822
* [WebAssembly] v8x16.shuffleThomas Lively2018-09-074-0/+95
| | | | | | | | | | | | | | | | | | Summary: Since the shuffle mask is not exposed as an operand in the native ISel DAG, create a new WebAssembly ISD node exposing the mask. The mask is lowered as sixteen immediate byte indices no matter what type the original vector shuffle was operating on. This CL depends on D51656 Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51659 llvm-svn: 341718
* [WebAssembly] Change SIMD lane indices to vec_i8imm_opThomas Lively2018-09-071-4/+4
| | | | | | | | | | | | Summary: To explicitly opt out of LEB encoding for these immediates. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51766 llvm-svn: 341707
* [WebAssembly] clang-format (NFC)Heejin Ahn2018-09-0537-549/+652
| | | | | | | | | | | | Summary: This patch runs clang-format on all wasm-only files. Reviewers: aardappel, dschuff, sunfish, tlively Subscribers: MatzeB, sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D51447 llvm-svn: 341439
* [WebAssembly] Fixed stale assert message in WebAssemblyMCInstLowerWouter van Oortmerssen2018-09-041-1/+1
| | | | llvm-svn: 341423
* [WebAssembly][NFC] Fix formatting and testsThomas Lively2018-09-041-1/+1
| | | | | | | | | | | | Summary: Small fixes Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51656 llvm-svn: 341411
* [WebAssembly] Fix operand rewriting in inline asm lowering.Dan Gohman2018-09-041-4/+2
| | | | | | | | | | | Use MachineOperand::ChangeToImmediate rather than reassigning MachineOperands to new values created from MachineOperand::CreateImm, so that their parent pointers are preserved. This fixes "Instruction has operand with wrong parent set" errors reported by the MachineVerifier. llvm-svn: 341389
* [WebAssembly] Update utility functions with SIMD typesThomas Lively2018-08-301-0/+28
| | | | | | | | | | Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51516 llvm-svn: 341131
* [WebAssembly] Vector conversionsThomas Lively2018-08-301-0/+11
| | | | | | | | | | | | | | Summary: Lowers away bitconverts between vector types. This CL depends on D51383. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51498 llvm-svn: 341128
* [WebAssembly] SIMD loads and storesThomas Lively2018-08-302-1/+69
| | | | | | | | | | | | Summary: Reuse the patterns from WebAssemblyInstrMemory.td. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51383 llvm-svn: 341127
* [WebAssembly] Made disassembler only use stack instructions.Wouter van Oortmerssen2018-08-301-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Now uses the StackBased bit from the tablegen defs to identify stack instructions (and ignore register based or non-wasm instructions). Also changed how we store operands, since we now have up to 16 of them per instruction. To not cause static data bloat, these are compressed into a tiny table. + a few other cleanups. Tested: - MCTest - llvm-lit -v `find test -name WebAssembly` Reviewers: dschuff, jgravelle-google, sunfish, tlively Subscribers: sbc100, aheejin, llvm-commits Differential Revision: https://reviews.llvm.org/D51320 llvm-svn: 341081
* [WebAssembly] Be a little more conservative in WebAssemblyFixFunctionBitcastsSam Clegg2018-08-301-7/+27
| | | | | | | | | | | | | | We don't have enough information to know if struct types being bitcast will cause validation failures or not, so be conservative and allow such cases to persist (fot now). Fixes: https://bugs.llvm.org/show_bug.cgi?id=38711 Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51460 llvm-svn: 341010
* [WebAssembly][NFC] Document stackifier tablegen backendThomas Lively2018-08-281-2/+7
| | | | | | | | | | | | | | Summary: Add comments to help readers avoid having to read tablegen backends to understand the code. Also remove unecessary breaks from the output. Reviewers: dschuff, aheejin Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51371 llvm-svn: 340864
* [WebAssembly] v128.notThomas Lively2018-08-281-0/+17
| | | | | | Implementation and tests. llvm-svn: 340857
* [WebAssembly] Use getCalleeOpNo utility function (NFC)Heejin Ahn2018-08-281-14/+2
| | | | | | | | | | Reviewers: tlively Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51366 llvm-svn: 340848
* [WebAssembly] TableGen backend for stackifying instructionsThomas Lively2018-08-272-356/+6
| | | | | | | | | | | | | | | | | Summary: The new stackification backend generates the giant switch statement used to translate instructions to their stackified forms. I did this because it was more interesting than adding all the different vector versions of the various SIMD instructions to the switch statment manually. Reviewers: aardappel, aheejin, dschuff Subscribers: mgorny, sbc100, jgravelle-google, sunfish, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D51318 llvm-svn: 340781
* [WebAssembly] Added default stack-only instruction mode for MC.Wouter van Oortmerssen2018-08-279-244/+573
| | | | | | | | | | | | | | | | | | | | | Summary: Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D51241 llvm-svn: 340750
* [WebAssembly] Prioritize splats over v128.constsThomas Lively2018-08-231-0/+2
| | | | | | | | | | | | | | Summary: Splats are fewer bytes than v128.consts, so use them when either could apply. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51179 llvm-svn: 340569
* [WebAssembly] SIMD Bitwise binary arithmeticThomas Lively2018-08-231-0/+18
| | | | | | | | | | | | Summary: AND, OR, and XOR. This CL depends on D51113. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51136 llvm-svn: 340505
* [WebAssembly][NFC] Reorganize SIMD instructionsThomas Lively2018-08-231-135/+96
| | | | | | | | | | | | | | | Summary: Reorganize WebAssemblyInstrSIMD.td to put all of the instruction definitions together, making it easier to see which instructions have been implemented already. Depends on D51143. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51113 llvm-svn: 340504
* [WebAssembly][NFC] Move specific instruction formats to specific filesThomas Lively2018-08-235-117/+121
| | | | | | | | | | | | | | Summary: WebAssemblyInstrFormats.td retains only multiclasses that are used in multiple other tablegen files. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D51143 llvm-svn: 340503
* [WebAssembly] Arbitrary BUILD_VECTOR and remove i64x2.mulThomas Lively2018-08-223-2/+121
| | | | | | | | | | | | | | | | | | Summary: This CL adds support for arbitrary BUILD_VECTORS, i.e. not splats and not consts. This is the last feature needed to properly lower v2i64 multiplies without a i64x2.mul instruction (which is not in the spec), so i64x2.mul is removed as well. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51082 Remove unnecessary condition and fix whitespace llvm-svn: 340472
* [WebAssembly] Don't write SP back when prolog is generated only for EHHeejin Ahn2018-08-223-5/+25
| | | | | | | | | | | | | | | Summary: When we don't actually have stack-allocated variables but need SP only to support EH, we don't need to write SP back in the epilog, because we don't bump down the stack pointer. Reviewers: dschuff Subscribers: jgravelle-google, sbc100, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51114 llvm-svn: 340454
* [WebAssembly] Remove MachineFrameInfo arg from checking functions (NFC)Heejin Ahn2018-08-222-13/+12
| | | | | | | | | | | | | | | | | | Summary: There are several functions in the form of `has***` or `needs***` in `WebAssemblyFrameLowering` and its `MachineFrameInfo` argument can be obtained from `MachineFunction` so it is not necessarily has to be passed from a caller. Also, it is more in line with other overriden fuctions like `hasBP` or `hasReservedCallFrame`, which also take only `MachineFunction` argument. Reviewers: dschuff Subscribers: sbc100, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51116 llvm-svn: 340438
* [WebAssembly] Add hasSideEffects flag to catch instructionsHeejin Ahn2018-08-221-1/+1
| | | | | | | | | | | | | | | Summary: `catch` instruction certainly has rather huge side effects and the flag was missing. At the moment this does not change any unit tests we currently have. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50919 llvm-svn: 340433
* [WebAssembly] Fix typos in mem.grow/memory.grow opcodesHeejin Ahn2018-08-221-2/+2
| | | | | | This should be not 0x3f but 0x40. llvm-svn: 340373
* [WebAssembly] Change comments on SP writing back (NFC)Heejin Ahn2018-08-222-3/+5
| | | | | | | | | | | | Summary: We now write back not to memory but to __stack_pointer global. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51074 llvm-svn: 340372
* [WebAssembly] Restore __stack_pointer after catch instructionsHeejin Ahn2018-08-216-6/+109
| | | | | | | | | | | | | | | Summary: After the stack is unwound due to a thrown exception, the `__stack_pointer` global can point to an invalid address. This inserts instructions that restore `__stack_pointer` global. Reviewers: jgravelle-google, dschuff Subscribers: mgorny, sbc100, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50980 llvm-svn: 340339
* [WebAssembly] v128.constThomas Lively2018-08-216-17/+141
| | | | | | | | | | | | | | | | Summary: This CL implements v128.const for each vector type. New operand types are added to ensure the vector contents can be serialized without LEB encoding. Tests are added for instruction selection, encoding, assembly and disassembly. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50873 llvm-svn: 340336
* [WebAssembly] Change writeSPToMemory to writeSPToGlobal (NFC)Heejin Ahn2018-08-211-4/+4
| | | | | | | | | | | | Summary: SP is now a __stack_pointer global and not a memory address anymore. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51046 llvm-svn: 340328
* [WebAssembly] Add isEHScopeReturn instruction propertyHeejin Ahn2018-08-211-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | Summary: So far, `isReturn` property is used to mean both a return instruction from a functon and the end of an EH scope, a scope that starts with a EH scope entry BB and ends with a catchret or a cleanupret instruction. Because WinEH uses funclets, all EH-scope-ending instructions are also real return instruction from a function. But for wasm, they only serve as the end marker of an EH scope but not a return instruction that exits a function. This mismatch caused incorrect prolog and epilog generation in wasm EH scopes. This patch fixes this. This patch is in the same vein with rL333045, which splits `MachineBasicBlock::isEHFuncletEntry` into `isEHFuncletEntry` and `isEHScopeEntry`. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50653 llvm-svn: 340325
* [WebAssembly] Revert type of wake count in atomic.wake to i32Heejin Ahn2018-08-201-18/+18
| | | | | | | | | | | | | | Summary: We decided to revert this from i64 to i32 in Nov 28 CG meeting. Fixes PR38632. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D51010 llvm-svn: 340234
* [WebAssembly] Remove an unused argument from writeSPToMemory (NFC)Heejin Ahn2018-08-201-8/+5
| | | | | | | | | | Reviewers: dschuff Subscribers: dschuff, sbc100, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50933 llvm-svn: 340230
* [WebAssembly] Modify LateEHPrepare one-line description (NFC)Heejin Ahn2018-08-171-1/+1
| | | | llvm-svn: 339972
* [WebAssembly] CFG stackify support for exception handlingHeejin Ahn2018-08-161-108/+542
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This adds support for exception handling to CFGStackify pass. This only adds TRY / END_TRY markers and DOES NOT yet fix unwind mismatches that can be created by the linearization of the CFG into the structural wasm format. The mismatch fix will be added by following patches. In detail, this patch - Added support for TRY / END_TRY markers to support EH - Changed many static functions into class member functions as they take too many arguments now - Added several more bookeeping data structures - Refactored routines that decide where to insert markers, because without refactoring this got too complicated as we added support for new kinds of markers (TRY/END_TRY). - Rewrote rethrow instructions' BB arguments to relative depths in EH pad stack. Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D48273 llvm-svn: 339967
* [WebAssembly] Remove temporary workaround for function bitcastsJacob Gravelle2018-08-161-5/+0
| | | | | | | | | | | | | | Summary: EM_ASM no longer is lowered as varargs in C, so this workaround is obsolete. Reviewers: dschuff, sunfish Subscribers: sbc100, aheejin, llvm-commits Differential Revision: https://reviews.llvm.org/D50859 llvm-svn: 339925
* [WebAssembly][NFC] Standardize SIMD multiclass formatThomas Lively2018-08-151-36/+30
| | | | | | | | | | | | | | Summary: This CL changes the ExtractLane ISEL multiclass to more closely mirror the structure of the splat and replace_lane multiclasses. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50794 llvm-svn: 339801
* [WebAssembly] Test commitThomas Lively2018-08-151-2/+1
| | | | | | Changes a comment and some whitespace to test commit access. llvm-svn: 339798
* [WebAssembly] SIMD replace_laneDerek Schuff2018-08-151-1/+22
| | | | | | | | | | Implement and test replace_lane instructions. Patch by Thomas Lively Differential Revision: https://reviews.llvm.org/D50750 llvm-svn: 339786
* [WebAssembly] SIMD SplatsDerek Schuff2018-08-151-0/+28
| | | | | | | | | | Implement and test SIMD splat ops. Patch by Thomas Lively Differential Revision: https://reviews.llvm.org/D50741 llvm-svn: 339744
* [WebAssembly] Fix encoding of non-SIMD vector-typed instructionsHeejin Ahn2018-08-142-29/+32
| | | | | | | | | | | | | | | | | | | Previously SIMD_I was the same as a normal instruction except for the addition of a HasSIM128 predicate. However, rL339186 changed the encoding of SIMD_I instructions to automatically contain the SIMD prefix byte. This broke the encoding of non-SIMD vector-typed instructions, which had instantiated SIMD_I. This CL corrects this error. Reviewers: aheejin Subscribers: sunfish, jgravelle-google, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D50682 Patch by Thomas Lively (tlively) llvm-svn: 339710
* [WebAssembly] SIMD extract_laneHeejin Ahn2018-08-141-2/+62
| | | | | | | | | | | | | | | | | Implement instruction selection for all versions of the extract_lane instruction. Use explicit sext/zext to differentiate between extract_lane_s and extract_lane_u for applicable types, otherwise default to extract_lane_u. Reviewers: aheejin Subscribers: sunfish, jgravelle-google, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D50597 Patch by Thomas Lively (tlively) llvm-svn: 339707
* Revert "[WebAssembly] Added default stack-only instruction mode for MC."Wouter van Oortmerssen2018-08-136-487/+256
| | | | | | This reverts commit 917a99b71ce21c975be7bfbf66f4040f965d9f3c. llvm-svn: 339630
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