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| author | Thomas Lively <tlively@google.com> | 2018-09-07 20:59:50 +0000 |
|---|---|---|
| committer | Thomas Lively <tlively@google.com> | 2018-09-07 20:59:50 +0000 |
| commit | 653278f80191a725528b767ecf4d7c47399630ca (patch) | |
| tree | 558efa51865d3aaa300cf452bb838d07d258c6c9 /llvm/lib/Target/WebAssembly | |
| parent | 287a3be3799738f66582a594210322cbe7c1e186 (diff) | |
| download | bcm5719-llvm-653278f80191a725528b767ecf4d7c47399630ca.tar.gz bcm5719-llvm-653278f80191a725528b767ecf4d7c47399630ca.zip | |
[WebAssembly] Change SIMD lane indices to vec_i8imm_op
Summary: To explicitly opt out of LEB encoding for these immediates.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D51766
llvm-svn: 341707
Diffstat (limited to 'llvm/lib/Target/WebAssembly')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index 4acc6507588..96c2ad54af5 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -44,8 +44,8 @@ multiclass ExtractLane<ValueType vec_t, string vec, ImmLeaf imm_t, WebAssemblyRegClass reg_t, bits<32> simdop, string suffix = "", SDNode extract = vector_extract> { defm EXTRACT_LANE_#vec_t#suffix : - SIMD_I<(outs reg_t:$dst), (ins V128:$vec, i32imm_op:$idx), - (outs), (ins i32imm_op:$idx), + SIMD_I<(outs reg_t:$dst), (ins V128:$vec, vec_i8imm_op:$idx), + (outs), (ins vec_i8imm_op:$idx), [(set reg_t:$dst, (extract (vec_t V128:$vec), (i32 imm_t:$idx)))], vec#".extract_lane"#suffix#"\t$dst, $vec, $idx", vec#".extract_lane"#suffix#"\t$idx", simdop>; @@ -80,8 +80,8 @@ multiclass ReplaceLane<ValueType vec_t, string vec, ImmLeaf imm_t, WebAssemblyRegClass reg_t, ValueType lane_t, bits<32> simdop> { defm REPLACE_LANE_#vec_t : - SIMD_I<(outs V128:$dst), (ins V128:$vec, i32imm_op:$idx, reg_t:$x), - (outs), (ins i32imm_op:$idx), + SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, reg_t:$x), + (outs), (ins vec_i8imm_op:$idx), [(set V128:$dst, (vector_insert (vec_t V128:$vec), (lane_t reg_t:$x), (i32 imm_t:$idx)))], vec#".replace_lane\t$dst, $vec, $idx, $x", |
