| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
| |
llvm-svn: 254271
|
|
|
|
| |
llvm-svn: 254104
|
|
|
|
|
|
|
|
|
|
| |
Instead of trying to move ARGUMENT instructions back up to the top after
they've been scheduled or sunk down, use a fake physical register to
create a liveness constraint that prevents ARGUMENT instructions from
moving down in the first place. This is still not entirely ideal, however
it is more robust than letting them move and moving them back.
llvm-svn: 254084
|
|
|
|
|
|
| |
operands.
llvm-svn: 253468
|
|
|
|
|
|
| |
This seems to be the most popular convention among the other backends.
llvm-svn: 253172
|
|
|
|
|
|
| |
Noticed by dschff in http://reviews.llvm.org/rL252203
llvm-svn: 252208
|
|
|
|
|
|
|
|
|
| |
Mangling type information into MachineInstr opcode names was a temporary
measure, and it's starting to get hairy. At the same time, the MC instruction
printer wants to use AsmString strings for printing. This patch takes the
first step, starting the process of adding AsmStrings for instructions.
llvm-svn: 252203
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary: The spec uses "or" for inclusive-or and "xor" for exclusive-or
Reviewers: sunfish
Subscribers: jfb, llvm-commits, dschuff
Differential Revision: http://reviews.llvm.org/D14362
llvm-svn: 252174
|
|
|
|
| |
llvm-svn: 252003
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
Add support for wasm's select operator, and lower LLVM's select DAG node
to it.
Reviewers: sunfish
Subscribers: dschuff, llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D14295
llvm-svn: 252002
|
|
|
|
|
|
|
| |
br_if shouldn't start with a dot.
div and rem went from prefix u/s to suffix.
llvm-svn: 250972
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary: It has also slightly changed.
Reviewers: binji
Subscribers: jfb, dschuff, llvm-commits, sunfish
Differential Revision: http://reviews.llvm.org/D13837
llvm-svn: 250591
|
|
|
|
| |
llvm-svn: 248644
|
|
|
|
|
|
| |
Renamed from: https://github.com/WebAssembly/design/pull/332
llvm-svn: 247028
|
|
|
|
| |
llvm-svn: 245851
|
|
|
|
|
|
|
|
|
|
|
|
| |
Some of the FP comparisons (ueq, one, ult, ule, ugt, uge) are currently broken, I'll fix them in a follow-up.
Reviewers: sunfish
Subscribers: llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11924
llvm-svn: 244665
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary: This patch has the most basic instruction codegen for 32 and 64 bit int/fp.
Reviewers: sunfish
Subscribers: llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11193
llvm-svn: 242201
|
|
Summary:
This code is based on AArch64 for modern backend good practice, and NVPTX for
virtual ISA concerns.
Reviewers: sunfish
Subscribers: aemerson, llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11070
llvm-svn: 241923
|