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* [SystemZ] Fix wrong-code generation for certain always-false conditionsUlrich Weigand2016-02-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | We've found another bug in the code generation logic conditions for a certain class of always-false conditions, those of the form if ((a & 1) < 0) These only reach the back end when compiling without optimization. The bug was introduced by the choice of using TEST UNDER MASK to implement a check for if ((a & MASK) < VAL) as if ((a & MASK) == 0) where VAL is less than the the lowest bit of MASK. This is correct in all cases except for VAL == 0, in which case the original condition is always false, but the replacement isn't. Fixed by excluding that particular case. llvm-svn: 259381
* Rename TargetSelectionDAGInfo into SelectionDAGTargetInfo and move it to ↵Benjamin Kramer2016-01-272-4/+4
| | | | | | | | CodeGen/ It's a SelectionDAG thing, not a Target thing. llvm-svn: 258939
* Move MCTargetAsmParser.h to llvm/MC/MCParser where it belongs.Benjamin Kramer2016-01-271-1/+1
| | | | llvm-svn: 258917
* Remove autoconf supportChris Bieneman2016-01-266-107/+0
| | | | | | | | | | | | | | | | Summary: This patch is provided in preparation for removing autoconf on 1/26. The proposal to remove autoconf on 1/26 was discussed on the llvm-dev thread here: http://lists.llvm.org/pipermail/llvm-dev/2016-January/093875.html "I felt a great disturbance in the [build system], as if millions of [makefiles] suddenly cried out in terror and were suddenly silenced. I fear something [amazing] has happened." - Obi Wan Kenobi Reviewers: chandlerc, grosbach, bob.wilson, tstellarAMD, echristo, whitequark Subscribers: chfast, simoncook, emaste, jholewinski, tberghammer, jfb, danalbert, srhines, arsenm, dschuff, jyknight, dsanders, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D16471 llvm-svn: 258861
* Reflect the MC/MCDisassembler split on the include/ level.Benjamin Kramer2016-01-261-1/+1
| | | | | | No functional change, just moving code around. llvm-svn: 258818
* [SystemZ] Fix bad instruction nameJonas Paulsson2016-01-151-1/+1
| | | | | | | | SLGBR -> SLBGR Reviewed by Ulrich Weigand llvm-svn: 257874
* Convert a few assert failures into proper errors.Rafael Espindola2016-01-131-3/+4
| | | | | | Fixes PR25944. llvm-svn: 257697
* [SystemZ] Add hasSideEffects flag on Serialize instruction.Jonas Paulsson2016-01-071-0/+3
| | | | | | | | | | Serialize will perform a hardware serialization operation, and is acting as a memory barrier. Therefore it must have the hasSideEffects flag set so it will be treated as a global memory object. Reviewed by Ulrich Weigand llvm-svn: 257036
* Remove extra forward declarations and scrub includes for all in tree ↵Craig Topper2015-12-251-1/+0
| | | | | | InstPrinters. NFC llvm-svn: 256427
* Avoid explicit relocation sorting most of the time.Rafael Espindola2015-12-171-16/+0
| | | | | | | | | | These days relocations are created and stored in a deterministic way. The order they are created is also suitable for the .o file, so we don't need an explicit sort. The last remaining exception is MIPS. llvm-svn: 255902
* Always sort by offset first. NFC.Rafael Espindola2015-12-171-3/+0
| | | | | | | Every target changing sortRelocs was first calling the parent implementation. Just run that first. llvm-svn: 255898
* [SystemZ] Sort relocs to avoid code corruption by linker optimizationUlrich Weigand2015-12-161-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SystemZ linkers provide an optimization to transform a general- or local-dynamic TLS sequence into an initial-exec sequence if possible. Do do that, the compiler generates a function call to __tls_get_offset, which is a brasl instruction annotated with *two* relocations: - a R_390_PLT32DBL to install __tls_get_offset as branch target - a R_390_TLS_GDCALL / R_390_TLS_LDCALL to inform the linker that the TLS optimization should be performed if possible If the optimization is performed, the brasl is replaced by an ld load instruction. However, *both* relocs are processed independently by the linker. Therefore it is crucial that the R_390_PLT32DBL is processed *first* (installing the branch target for the brasl) and the R_390_TLS_GDCALL is processed *second* (replacing the whole brasl with an ld). If the relocs are swapped, the linker will first replace the brasl with an ld, and *then* install the __tls_get_offset branch target offset. Since ld has a different layout than brasl, this may even result in a completely different (or invalid) instruction; in any case, the resulting code is corrupted. Unfortunately, the way the MC common code sorts relocations causes these two to *always* end up the wrong way around, resulting in wrong code generation by the linker and crashes. This patch overrides the sortRelocs routine to detect this particular pair of relocs and enforce the required order. llvm-svn: 255787
* [SystemZ] Fix assertion failure in adjustSubwordCmpUlrich Weigand2015-12-161-2/+2
| | | | | | | | | | | | | | | | | | | | When comparing a zero-extended value against a constant small enough to be in range of the inner type, it doesn't matter whether a signed or unsigned compare operation (for the outer type) is being used. This is why the code in adjustSubwordCmp had this assertion: assert(C.ICmpType == SystemZICMP::Any && "Signedness shouldn't matter here."); assuming the the caller had already detected that fact. However, it turns out that there cases, in particular with always-true or always- false conditions that have not been eliminated when compiling at -O0, where this is not true. Instead of failing an assertion if C.ICmpType is not SystemZICMP::Any here, we can simply *set* it safely to SystemZICMP::Any, however. llvm-svn: 255786
* [PostRA scheduling] Allow a target to do scheduling when it wants post RA.Jonas Paulsson2015-12-102-0/+14
| | | | | | | | | | | | | | SystemZ needs to do its scheduling after branch relaxation, which can only happen after block placement, and therefore the standard PostRAScheduler point in the pass sequence is too early. TargetMachine::targetSchedulesPostRAScheduling() is a new method that signals on returning true that target will insert the final scheduling pass on its own. Reviewed by Hal Finkel llvm-svn: 255234
* [SystemZ] Bugfix: Don't add CC twice to new three-address instruction.Jonas Paulsson2015-12-041-4/+10
| | | | | | | | | | | Since BuildMI() automatically adds the implicit operands for a new instruction, adding the old instructions CC operand resulted in that there were two CC imp-def operands, where only one was marked as dead. This caused buildSchedGraph() to miss dependencies on the CC reg. Review by Ulrich Weigand llvm-svn: 254714
* [Stack realignment] Handling of aligned allocas.Jonas Paulsson2015-11-282-2/+33
| | | | | | | | | | | | | | | | | | | | This patch implements dynamic realignment of stack objects for targets with a non-realigned stack pointer. Behaviour in FunctionLoweringInfo is changed so that for a target that has StackRealignable set to false, over-aligned static allocas are considered to be variable-sized objects and are handled with DYNAMIC_STACKALLOC nodes. It would be good to group aligned allocas into a single big alloca as an optimization, but this is yet todo. SystemZ benefits from this, due to its stack frame layout. New tests SystemZ/alloca-03.ll for aligned allocas, and SystemZ/alloca-04.ll for "no-realign-stack" attribute on functions. Review and help from Ulrich Weigand and Hal Finkel. llvm-svn: 254227
* Drop prelink support.Rafael Espindola2015-11-172-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way prelink used to work was * The compiler decides if a given section only has relocations that are know to point to the same DSO. If so, it names it .data.rel.ro.local<something>. * The static linker puts all of these together. * The prelinker program assigns addresses to each library and resolves the local relocations. There are many problems with this: * It is incompatible with address space randomization. * The information passed by the compiler is redundant. The linker knows if a given relocation is in the same DSO or not. If could sort by that if so desired. * There are newer ways of speeding up DSO (gnu hash for example). * Even if we want to implement this again in the compiler, the previous implementation is pretty broken. It talks about relocations that are "resolved by the static linker". If they are resolved, there are none left for the prelinker. What one needs to track is if an expression will require only dynamic relocations that point to the same DSO. At this point it looks like the prelinker is an historical curiosity. For example, fedora has retired it because it failed to build for two releases (http://pkgs.fedoraproject.org/cgit/prelink.git/commit/?id=eb43100a8331d91c801ee3dcdb0a0bb9babfdc1f) This patch removes support for it. That is, it stops printing the ".local" sections. llvm-svn: 253280
* Reduce the size of MCRelaxableFragment.Akira Hatanaka2015-11-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | MCRelaxableFragment previously kept a copy of MCSubtargetInfo and MCInst to enable re-encoding the MCInst later during relaxation. A copy of MCSubtargetInfo (instead of a reference or pointer) was needed because the feature bits could be modified by the parser. This commit replaces the MCSubtargetInfo copy in MCRelaxableFragment with a constant reference to MCSubtargetInfo. The copies of MCSubtargetInfo are kept in MCContext, and the target parsers are now responsible for asking MCContext to provide a copy whenever the feature bits of MCSubtargetInfo have to be toggled. With this patch, I saw a 4% reduction in peak memory usage when I compiled verify-uselistorder.lto.bc using llc. rdar://problem/21736951 Differential Revision: http://reviews.llvm.org/D14346 llvm-svn: 253127
* [MCTargetAsmParser] Move the member varialbes that referenceAkira Hatanaka2015-11-141-4/+3
| | | | | | | | | | MCSubtargetInfo in the subclasses into MCTargetAsmParser and define a member function getSTI. This is done in preparation for making changes to shrink the size of MCRelaxableFragment. (see http://reviews.llvm.org/D14346). llvm-svn: 253124
* [SystemZ] Simplify boolean conditional return statementsUlrich Weigand2015-11-132-12/+4
| | | | | | | | | Use clang-tidy to simplify conditonal return statements. Author: LegalizeAdulthood Differential Revision: http://reviews.llvm.org/D9986 llvm-svn: 253038
* [WinEH] Update exception pointer registersJoseph Tremoulet2015-11-072-2/+14
| | | | | | | | | | | | | | | | | | | | Summary: The CLR's personality routine passes these in rdx/edx, not rax/eax. Make getExceptionPointerRegister a virtual method parameterized by personality function to allow making this distinction. Similarly make getExceptionSelectorRegister a virtual method parameterized by personality function, for symmetry. Reviewers: pgavlin, majnemer, rnk Subscribers: jyknight, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14344 llvm-svn: 252383
* Remove windows line endings introduced by r252177. NFC.Tim Northover2015-11-051-17/+17
| | | | llvm-svn: 252217
* [DebugInfo] Fix ARM/AArch64 prologue_end position. Related to D11268.Oleg Ranevskyy2015-11-051-14/+17
| | | | | | | | | | | | | | | | | | | Summary: This review is related to another review request http://reviews.llvm.org/D11268, does the same and merely fixes a couple of issues with it. D11268 is quite old and has merge conflicts against the current trunk. This request - rebases D11268 onto the new trunk; - resolves the merge conflicts; - fixes the prologue_end tests, which do not pass due to the subprogram definitions not marked as distinct. Reviewers: echristo, rengolin, kubabrecka Subscribers: aemerson, rengolin, jyknight, dsanders, llvm-commits, asl Differential Revision: http://reviews.llvm.org/D14338 llvm-svn: 252177
* Untabify.NAKAMURA Takumi2015-11-023-7/+7
| | | | llvm-svn: 251769
* [SystemZ] Make the CCRegs regclass non-allocatable.Jonas Paulsson2015-10-293-4/+6
| | | | | | | | | | | | | | | | | | | | | This was discovered to be necessary while running memchr-01.ll with -verify-machinstrs, because it is not allowed to have a phys reg live accross block boundaries while on SSA form, if the register is allocatable (expect in entry block and landing pads). In this test case, stringRRE pseudos are expanded after isel by adding a loop block which produces a live out CC register. To make the test pass, it was also necessary to not say that StringRRELoop pseudo uses R0L, this is only true for the StringRRE opcode. -verify-machineinstrs added to memchr-01.ll test. New test case int-cmp-51.ll to test that MachineCSE can eliminate an identical compare (which it couldn't do before). Reviewed by Ulrich Weigand llvm-svn: 251634
* Put global classes into the appropriate namespace.Benjamin Kramer2015-10-281-4/+4
| | | | | | | Most of the cases belong into an anonymous namespace. No functionality change intended. llvm-svn: 251515
* [SystemZ] LTGFR use regclass should be GR32, not GR64.Jonas Paulsson2015-10-261-1/+1
| | | | | | | Discovered by testing int-cmp-44.ll with -verify-machineinstrs (added to test run). llvm-svn: 251299
* [SystemZ] Also clear kill flag for index reg in splitMove().Jonas Paulsson2015-10-261-1/+3
| | | | | | | Discovered by running fp-move-05.ll with -verify-machineinstrs (added to test case run). llvm-svn: 251298
* [SystemZ] Don't forget the CC def op on LTEBRCompare pseudosJonas Paulsson2015-10-261-1/+1
| | | | | | | Discovered by running fp-cmp-02.ll with -verify-machineinstrs (now added to test run). llvm-svn: 251297
* [SystemZ] Tie operands in SystemZShorteInst if MI becomes 2-address.Jonas Paulsson2015-10-261-1/+10
| | | | | | | | Discovered by testing fp-add-02.ll with -verify-machineinstrs. Test case updated to always run with -verify-machineinstrs. llvm-svn: 251296
* [SystemZ] Use LivePhysRegs helper class in SystemZShortenInst.cpp.Jonas Paulsson2015-10-201-80/+35
| | | | | | | | | Don't use home brewed liveness tracking code for phys regs, since this class does the job. Reviewed by Ulrich Weigand. llvm-svn: 250829
* SystemZ: Remove implicit ilist iterator conversion, NFCDuncan P. N. Exon Smith2015-10-201-1/+1
| | | | llvm-svn: 250790
* [SystemZ] Fixes in the backend I/R.Jonas Paulsson2015-10-102-3/+5
| | | | | | | | | | | | | | | expandPostRAPseudo(): STX -> 2 * STD: The first STD should not have the kill flag set for the address. SystemZElimCompare: BRC -> BRCT conversion: Don't forget to remove the CC<use,kill> operand. Needed to make SystemZ/asm-17.ll pass with -verify-machineinstrs, which now runs with this flag. Reviewed by Ulrich Weigand. llvm-svn: 249945
* [SystemZ] Remove unused code in SystemZElimCompare.cppJonas Paulsson2015-10-091-19/+7
| | | | | | | The Reference IndirectDef and IndirectUse members were unused and therefore removed. llvm-svn: 249824
* [SystemZ] Remove superfluous braces in SystemZShortenInst.cppJonas Paulsson2015-10-091-2/+2
| | | | llvm-svn: 249812
* [SystemZ] Minor bugfixes.Jonas Paulsson2015-10-092-4/+5
| | | | | | | | | | | | | | LLCH, LLHH and CLIH had the wrong register classes for the def-operand. Tie operands if changing opcode to an instruction with tied ops. Comment typo fix. These fixes were needed in order to make regression test case SystemZ/asm-18.ll pass with -verify-machineinstrs (not used by default). Reviewed by Ulrich Weigand. llvm-svn: 249811
* [SystemZ] Bugfix in SystemZAsmParser.cpp.Jonas Paulsson2015-10-091-4/+6
| | | | | | | | | Let parseRegister() allow RegFP Group if expecting RegV Group, since the %f register prefix yields the FP group even while used with vector instructions. Reviewed by Ulrich Weigand. llvm-svn: 249810
* [SystemZ] Fix another assertion failure in tryBuildVectorShuffleUlrich Weigand2015-10-081-1/+1
| | | | | | | | | | | | | | | | This fixes yet another scenario where tryBuildVectorShuffle would attempt to create a BUILD_VECTOR node with an invalid combination of types. This can happen if the incoming BUILD_VECTOR has elements of a type different from the vector element type, which is allowed in certain cases as long as they are all the same type. When one of these elements is used in the residual vector, and UNDEF elements are added to fill up the residual vector, those UNDEFs then have to use the type of the original element, not the vector element type, or else the resulting BUILD_VECTOR will have an invalid type combination. llvm-svn: 249706
* [SystemZ] SystemZElimCompare pass improved.Jonas Paulsson2015-10-082-5/+38
| | | | | | | | | | | | | | Compare elimination extended to recognize load-and-test instructions used for comparison and eliminate them the same way as with compare instructions. Test case fp-cmp-05.ll updated to expect optimized results now also for z13. The order of instruction shortening and compare elimination passes have been changed so that opcodes do not have to be handled in both passes. Reviewed by Ulrich Weigand. llvm-svn: 249666
* [SystemZ] Bugfix: check CC reg liveness in SystemZShortenInst.Jonas Paulsson2015-10-081-4/+25
| | | | | | | | | | | | | | The following instruction shortening transformations would introduce a definition of the CC reg, so therefore liveness of CC reg must be checked: WFADB -> ADBR WFSDB -> SDBR Also add the CC reg implicit def operand to the MI in case of change of opcode. Reviewed by Ulrich Weigand. llvm-svn: 249665
* [SystemZ] Use load-and-test for fp compare with 0 if vector support is present.Jonas Paulsson2015-10-083-3/+52
| | | | | | | | | Since the LTxBRCompare instructions can't be used with vector registers, a normal load-and-test instruction (with a modelled def operand) is used instead. Reviewed by Ulrich Weigand. llvm-svn: 249664
* [SystemZ] More minor fixing in SystemZElimCompare.cppJonas Paulsson2015-10-081-9/+5
| | | | | | | | Don't use subreg indices since they are not used after regalloc. Reviewed by Ulrich Weigand. llvm-svn: 249663
* [SystemZ] Minor fixes in SystemZElimCompare.cppJonas Paulsson2015-10-081-4/+3
| | | | | | Reviewed by Ulrich Weigand. llvm-svn: 249662
* [SystemZ] Add some generic (floating point support) load instructions.Jonas Paulsson2015-10-014-17/+37
| | | | | | | | | | | | | | | | | | | | | | Add generic instructions for load complement, load negative and load positive for fp32 and fp64, and let isel prefer them. They do not clobber CC, and so give scheduler more freedom. SystemZElimCompare pass will convert them when it can to the CC-setting variants. Regression tests updated to expect the new opcodes in places where the old ones where used. New test case SystemZ/fp-cmp-05.ll checks that SystemZCompareElim.cpp can handle the new opcodes. README.txt updated (bullet removed). Note that fp128 is not yet handled, because it is relatively rare, and is a bit trickier, because of the fact that l.dfr would operate on the sign bit of one of the subregisters of a fp128, but we would not want to copy the other sub-reg in case src and dst regs are not the same. Reviewed by Ulrich Weigand. llvm-svn: 249046
* [SystemZ] Add assembly instructions for obtaining clock values as well as ↵Ulrich Weigand2015-10-011-0/+20
| | | | | | | | | | | CPU features Provide assembler support for STCK, STCKF, STCKE, and STFLE. Author: joncmu Differential Revision: http://reviews.llvm.org/D13299 llvm-svn: 249015
* Prune trailing whitespaces.NAKAMURA Takumi2015-09-221-1/+1
| | | | llvm-svn: 248265
* Untabify.NAKAMURA Takumi2015-09-224-33/+28
| | | | llvm-svn: 248264
* [SystemZ] Fix expansion of ISD::FPOW and ISD::FSINCOSUlrich Weigand2015-09-211-0/+2
| | | | | | | | | | | | | The ISD::FPOW and ISD::FSINCOS opcodes default to Legal, but there is no legal instruction for those on SystemZ. This could cause LLVM internal errors. Fixed by setting the operation action to Expand for those opcodes. Also added test cases for all other LLVM IR intrinsics that should generate a library call. (Those already work correctly since the default operation action is fine.) llvm-svn: 248180
* constify the Function parameter to the TTI creation callback andEric Christopher2015-09-162-2/+2
| | | | | | propagate to all callers/users/etc. llvm-svn: 247864
* Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and ↵Daniel Sanders2015-09-156-15/+13
| | | | | | | | related. NFC. Eric has replied and has demanded the patch be reverted. llvm-svn: 247702
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