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| author | NAKAMURA Takumi <geek4civic@gmail.com> | 2015-09-22 11:19:03 +0000 |
|---|---|---|
| committer | NAKAMURA Takumi <geek4civic@gmail.com> | 2015-09-22 11:19:03 +0000 |
| commit | 10c80e79963f26b0c3d155506376a8c0ab4472bd (patch) | |
| tree | 9f38e9893543962e8852c546e99eb437300e66c6 /llvm/lib/Target/SystemZ | |
| parent | 0a7d0ad95fc1162f8266a48b88e223e24dcd4a90 (diff) | |
| download | bcm5719-llvm-10c80e79963f26b0c3d155506376a8c0ab4472bd.tar.gz bcm5719-llvm-10c80e79963f26b0c3d155506376a8c0ab4472bd.zip | |
Prune trailing whitespaces.
llvm-svn: 248265
Diffstat (limited to 'llvm/lib/Target/SystemZ')
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 6830e380c24..faf2e656ee2 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -2844,7 +2844,7 @@ SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op, } else if (DAG.ComputeNumSignBits(Op1) > 32) { Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1); Opcode = SystemZISD::SDIVREM32; - } else + } else Opcode = SystemZISD::SDIVREM64; // DSG(F) takes a 64-bit dividend, so the even register in the GR128 |
