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path: root/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
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* [SystemZ] Bugfix and improve the handling of CC values.Jonas Paulsson2019-12-201-0/+8
* [SystemZ] Improve verification of MachineOperands.Jonas Paulsson2019-12-161-0/+22
* Use MCRegister in copyPhysRegMatt Arsenault2019-11-111-14/+14
* Remove the AliasAnalysis argument in function areMemAccessesTriviallyDisjointChangpeng Fang2019-09-261-2/+1
* [SystemZ] Merge the SystemZExpandPseudo pass into SystemZPostRewrite.Jonas Paulsson2019-09-161-111/+11
* [SystemZ] Recognize INLINEASM_BR in backendJonas Paulsson2019-09-051-9/+13
* [SystemZ] Recognize INLINEASM_BR in backend.Jonas Paulsson2019-09-031-2/+2
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-15/+15
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-2/+3
* [SystemZ] Fix build bot failure after r365932Ulrich Weigand2019-07-121-2/+2
* [SystemZ] Add support for new cpu architecture - arch13Ulrich Weigand2019-07-121-4/+86
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-241-4/+4
* [SystemZ] Fix AHIMuxK pseudo expansion.Jonas Paulsson2019-06-181-4/+6
* [SystemZ, RegAlloc] Favor 3-address instructions during instruction selection.Jonas Paulsson2019-06-081-70/+48
* [CodeGen] Add "const" to MachineInstr::mayAliasBjorn Pettersson2019-04-191-1/+2
* [Hexagon, SystemZ] Be super conservative about atomicsPhilip Reames2019-02-241-1/+1
* [SystemZ] Do not return INT_MIN from strcmp/memcmpUlrich Weigand2019-02-061-74/+0
* [CodeGen][ARC][SystemZ][WebAssembly] Use MachineInstr::isInlineAsm in more pl...Craig Topper2019-02-041-1/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [SystemZ] Replace subreg_r with subreg_hKrzysztof Parzyszek2018-08-151-4/+4
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-091-2/+2
* [SystemZ] Handle SADDO et.al. and ADD/SUBCARRYUlrich Weigand2018-04-301-0/+30
* [SystemZ] Do not use glue to represent condition code dependenciesUlrich Weigand2018-04-301-0/+17
* Rename LiveIntervalAnalysis.h to LiveIntervals.hMatthias Braun2017-12-131-1/+1
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* [RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints.Jonas Paulsson2017-11-101-0/+6
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
* [SystemZ] Add support for IBM z14 processor (3/3)Ulrich Weigand2017-07-171-0/+31
* [SystemZ] Add support for IBM z14 processor (1/3)Ulrich Weigand2017-07-171-0/+1
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* [SystemZ] Fix register modelling in expandLoadStackGuard()Jonas Paulsson2017-05-241-16/+14
* [SystemZ] Make copyPhysReg() add impl-use operands of super reg.Jonas Paulsson2017-05-041-1/+7
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-4/+3
* [SystemZ] Update kill-flag in splitMove().Jonas Paulsson2017-04-241-2/+3
* [SystemZ] Make sure of correct regclasses in insertSelect()Jonas Paulsson2017-03-311-0/+6
* [SystemZ] Don't drop any operands in expandZExtPseudo()Jonas Paulsson2017-03-221-13/+18
* [SystemZ] Don't drop MO flags in foldMemoryOperandImpl()Jonas Paulsson2017-03-211-5/+5
* [SystemZ] Add use of super-reg in splitMove()Jonas Paulsson2017-03-171-1/+14
* Make TargetInstrInfo::isPredicable take a const reference, NFCKrzysztof Parzyszek2017-03-031-1/+1
* [SystemZ] Fix some Clang-tidy modernize and Include What You Use warnings; ot...Eugene Zelenko2017-01-241-9/+32
* [SystemZ] Proper handling of undef flag while expanding pseudo.Jonas Paulsson2017-01-181-6/+9
* [CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus2017-01-131-11/+12
* [SystemZ] Support load-and-trap instructionsUlrich Weigand2016-11-281-0/+19
* [SystemZ] Add remaining branch instructionsUlrich Weigand2016-11-281-0/+5
* [SystemZ] Improve use of conditional instructionsUlrich Weigand2016-11-281-36/+191
* [SystemZ] Support CL(G)T instructionsUlrich Weigand2016-11-111-0/+12
* [SystemZ] Model access registers as LLVM registersUlrich Weigand2016-11-081-2/+10
* [SystemZ] Post-RA scheduler implementationJonas Paulsson2016-10-201-0/+35
* Finish renaming remaining analyzeBranch functionsMatt Arsenault2016-09-141-2/+2
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-141-2/+2
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