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path: root/llvm/lib/Target/SystemZ/SystemZISelLowering.h
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* [FPEnv] Default NoFPExcept SDNodeFlag to falseUlrich Weigand2020-01-021-10/+26
* [SystemZ][FPEnv] Enable strict vector FP extends/truncationsUlrich Weigand2019-12-201-2/+2
* [FPEnv] Constrained FCmp intrinsicsUlrich Weigand2019-12-071-8/+14
* DAG: Add function context to isFMAFasterThanFMulAndFAddMatt Arsenault2019-11-191-1/+2
* [SystemZ] Fix typoUlrich Weigand2019-11-041-1/+1
* [SystemZ] Add support for new cpu architecture - arch13Ulrich Weigand2019-07-121-0/+10
* [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR...Simon Pilgrim2019-06-121-0/+1
* [TargetLowering] Add code size information on isFPImmLegal. NFCAdhemerval Zanella2019-03-181-1/+2
* Seperate volatility and atomicity/ordering in SelectionDAGPhilip Reames2019-02-271-0/+1
* [SystemZ] Wait with selection of legal vector/FP constants until Select().Jonas Paulsson2019-02-261-3/+22
* [SystemZ] Use VGM whenever possible to load FP immediates.Jonas Paulsson2019-02-121-1/+3
* [SystemZ] Improved handling of the @llvm.ctlz intrinsic.Jonas Paulsson2019-02-061-0/+1
* [SystemZ] Wait with VGBM selection until after DAGCombine2.Jonas Paulsson2019-02-061-4/+2
* [DAG][SystemZ] Define unwrapAddress for PCREL_WRAPPER.Nirav Dave2019-01-311-0/+2
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [SystemZ] Make better use of VLDEBUlrich Weigand2018-12-201-0/+1
* [SystemZ] Increase the number of VLREPsJonas Paulsson2018-11-131-0/+1
* [TargetLowering] Change TargetLoweringBase::getPreferredVectorAction to take ...Craig Topper2018-11-051-1/+1
* [SystemZ] Simplify LRV/STRV ISD nodesUlrich Weigand2018-10-301-12/+2
* [SystemZ] Improve handling and cost estimates of vector integer div/remJonas Paulsson2018-10-251-0/+1
* [SystemZ, TableGen] Fix shift count handlingUlrich Weigand2018-08-011-1/+0
* [SystemZ] Handle SADDO et.al. and ADD/SUBCARRYUlrich Weigand2018-04-301-0/+16
* [SystemZ] Do not use glue to represent condition code dependenciesUlrich Weigand2018-04-301-5/+5
* [SystemZ] Improve handling of Select pseudo-instructionsUlrich Weigand2018-04-301-2/+1
* [SystemZ] computeKnownBitsForTargetNode() / ComputeNumSignBitsForTargetNode()Jonas Paulsson2018-03-171-0/+6
* [SystemZ] Support stackmaps and patchpointsUlrich Weigand2018-03-021-0/+1
* [SystemZ] Directly use CC result of compare-and-swapUlrich Weigand2018-01-191-0/+2
* [SystemZ] Rework IPM sequence generationUlrich Weigand2018-01-191-0/+2
* [SystemZ] Implement computeKnownBitsForTargetNodeUlrich Weigand2018-01-191-0/+8
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* [SystemZ] Add support for the "o" inline asm constraintUlrich Weigand2017-11-091-0/+2
* [SystemZ] Custom-expand ATOMIC_CMP_AND_SWAP_WITH_SUCCESSUlrich Weigand2017-09-281-1/+5
* [LSR / TTI / SystemZ] Eliminate TargetTransformInfo::isFoldableMemAccess()Jonas Paulsson2017-08-091-1/+0
* [SystemZ] Add support for 128-bit atomic load/store/cmpxchgUlrich Weigand2017-08-041-0/+18
* [SystemZ, LoopStrengthReduce]Jonas Paulsson2017-07-211-1/+2
* [SystemZ] Add support for IBM z14 processor (2/3)Ulrich Weigand2017-07-171-0/+6
* [SystemZ] Add support for IBM z14 processor (1/3)Ulrich Weigand2017-07-171-0/+1
* [SystemZ] Simplify handling of 128-bit multiply/divide instructionUlrich Weigand2017-07-051-9/+6
* [SystemZ] Remove unnecessary serialization before volatile loadsUlrich Weigand2017-06-231-6/+0
* [SystemZ] Implement getRepRegClassFor()Jonas Paulsson2017-05-101-0/+2
* DAG: Make mayBeEmittedAsTailCall parameter constMatt Arsenault2017-04-181-1/+1
* [SystemZ] Check for presence of vector support in SystemZISelLoweringJonas Paulsson2017-04-071-0/+1
* [SystemZ] Improve use of conditional instructionsUlrich Weigand2016-11-281-1/+2
* [SystemZ] Model access registers as LLVM registersUlrich Weigand2016-11-081-4/+0
* getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-141-1/+1
* [LoopStrenghtReduce] Refactoring and addition of a new target cost function.Jonas Paulsson2016-08-171-0/+1
* [SystemZ] Remove AND mask of bottom 6 bits when result is used for shift/rotateElliot Colp2016-07-061-0/+1
* [SystemZ] Move misplaced SystemZ::TDC to non-memory opcode range.Marcin Koscielnicki2016-07-021-6/+6
* CodeGen: Use MachineInstr& in TargetLowering, NFCDuncan P. N. Exon Smith2016-06-301-21/+14
* [SystemZ] Split up PerformDAGCombine. [NFC]Marcin Koscielnicki2016-06-301-0/+7
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